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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-09-03 12:36:29 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-09-09 08:48:30 +0000 |
| commit | 0004a6a06073131d5785100b2d7b9b07ecee63af (patch) | |
| tree | 9a9445e966fb70da6f7790cac0ad6e84bd345eca | |
| parent | 59370dde2efec2d19280d8453407ea8feda20370 (diff) | |
| download | gem5-0004a6a06073131d5785100b2d7b9b07ecee63af.tar.xz | |
dev-arm: Writes to IGRPEN1_EL3 triggering update
Change-Id: I56804eb1bfc8913bd0d3cab05865a382bf270bc1
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20634
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
| -rw-r--r-- | src/dev/arm/gic_v3_cpu_interface.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/dev/arm/gic_v3_cpu_interface.cc b/src/dev/arm/gic_v3_cpu_interface.cc index 792337fe9..d7988e13d 100644 --- a/src/dev/arm/gic_v3_cpu_interface.cc +++ b/src/dev/arm/gic_v3_cpu_interface.cc @@ -1378,6 +1378,7 @@ Gicv3CPUInterface::setMiscReg(int misc_reg, RegVal val) MISCREG_ICC_IGRPEN1_EL1_S, icc_igrpen1_el3.EnableGrp1S); isa->setMiscRegNoEffect( MISCREG_ICC_IGRPEN1_EL1_NS, icc_igrpen1_el3.EnableGrp1NS); + updateDistributor(); return; } |