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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-09-02 15:28:58 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-09-06 20:00:34 +0000 |
| commit | 1e1d5e247ecc55dc3d92875ca5ec6ae70879d8c1 (patch) | |
| tree | 4d96d7b40b555524d74eaeda92bc45bb9e4a3f7a | |
| parent | 96fdb20871b16782ed405e58e9d9cc005d661b21 (diff) | |
| download | gem5-1e1d5e247ecc55dc3d92875ca5ec6ae70879d8c1.tar.xz | |
arch-arm: MISCREG_ICC_BPR1_EL1 using AA64 banking
Change-Id: Ib30c7a49490f05f88ddfd7572dd360cb92647f81
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20625
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
| -rw-r--r-- | src/arch/arm/miscregs.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc index 0bae01893..76a991746 100644 --- a/src/arch/arm/miscregs.cc +++ b/src/arch/arm/miscregs.cc @@ -4603,7 +4603,7 @@ ISA::initializeMiscRegMetadata() .allPrivileges().exceptUserMode().writes(0) .mapsTo(MISCREG_ICC_HPPIR1); InitReg(MISCREG_ICC_BPR1_EL1) - .banked() + .banked64() .mapsTo(MISCREG_ICC_BPR1); InitReg(MISCREG_ICC_BPR1_EL1_NS) .bankedChild() |