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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-08-20 20:48:29 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-09-06 20:00:34 +0000 |
| commit | 2a818db77ab5fe5cc7d716dd2aa88241550045a7 (patch) | |
| tree | 73e57fcf8296bb7244d4fbc5920888725072325c | |
| parent | 34f1b771ed911ac8dc9f02ded63add7de3c263ed (diff) | |
| download | gem5-2a818db77ab5fe5cc7d716dd2aa88241550045a7.tar.xz | |
arch-arm, dev-arm: MISCREG_ICC_IGRPEN1_EL1 using AA64 banking
Change-Id: Ic08ac1e7f3ebef408a83aa068ce15e9dfe2aa3cd
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20628
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
| -rw-r--r-- | src/arch/arm/miscregs.cc | 2 | ||||
| -rw-r--r-- | src/dev/arm/gic_v3_cpu_interface.cc | 4 |
2 files changed, 4 insertions, 2 deletions
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc index 81bc3efae..bffb4446a 100644 --- a/src/arch/arm/miscregs.cc +++ b/src/arch/arm/miscregs.cc @@ -4646,7 +4646,7 @@ ISA::initializeMiscRegMetadata() .allPrivileges().exceptUserMode() .mapsTo(MISCREG_ICC_IGRPEN0); InitReg(MISCREG_ICC_IGRPEN1_EL1) - .banked() + .banked64() .mapsTo(MISCREG_ICC_IGRPEN1); InitReg(MISCREG_ICC_IGRPEN1_EL1_NS) .bankedChild() diff --git a/src/dev/arm/gic_v3_cpu_interface.cc b/src/dev/arm/gic_v3_cpu_interface.cc index 0d444f165..b793f7c28 100644 --- a/src/dev/arm/gic_v3_cpu_interface.cc +++ b/src/dev/arm/gic_v3_cpu_interface.cc @@ -191,6 +191,7 @@ Gicv3CPUInterface::readMiscReg(int misc_reg) return readMiscReg(MISCREG_ICV_IGRPEN1_EL1); } + value = readBankedMiscReg(MISCREG_ICC_IGRPEN1_EL1); break; } @@ -1358,7 +1359,8 @@ Gicv3CPUInterface::setMiscReg(int misc_reg, RegVal val) icc_igrpen1_el3); } - break; + setBankedMiscReg(MISCREG_ICC_IGRPEN1_EL1, val); + return; } // Virtual Interrupt Group 1 Enable register |