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authorKarthik Sangaiah <karthik.sangaiah@arm.com>2015-07-15 14:43:35 +0100
committerKarthik Sangaiah <karthik.sangaiah@arm.com>2015-07-15 14:43:35 +0100
commit47326f54222af99d96ab57508449d1bb62d03842 (patch)
treef25d43e06bf0422610f7812a94a5f600270fa52b
parent6fa936b021ac4d3030d20de5d037f1e7dd902cd9 (diff)
downloadgem5-47326f54222af99d96ab57508449d1bb62d03842.tar.xz
arm: Bootloader fix for v8 over 16 cores
Previous code used a smaller 4 bit mask to test the MPIDR-EL1 register. The bitmask was extended to support greater than 16 cores.
-rw-r--r--system/arm/aarch64_bootloader/boot.S17
1 files changed, 13 insertions, 4 deletions
diff --git a/system/arm/aarch64_bootloader/boot.S b/system/arm/aarch64_bootloader/boot.S
index 78d9710d4..933d7ee8a 100644
--- a/system/arm/aarch64_bootloader/boot.S
+++ b/system/arm/aarch64_bootloader/boot.S
@@ -34,8 +34,12 @@ _start:
* registers.
*/
mrs x0, mpidr_el1
- tst x0, #15
- b.ne 1f // secondary CPU
+ // ARM MPIDR_EL1 bytes: Aff3 (AArch64), Stuff, Aff2, Aff1, Aff0
+ // Test the the MPIDR_EL1 register against 0xff00ffffff to
+ // extract the primary CPU.
+ ldr x1, =0xff00ffffff
+ tst x0, x1 // check for cpuid==zero
+ b.ne 1f // secondary CPU
ldr x1, =GIC_DIST_BASE // GICD_CTLR
mov w0, #3 // EnableGrp0 | EnableGrp1
@@ -77,8 +81,13 @@ start_ns:
mov x3, xzr
mrs x4, mpidr_el1
- tst x4, #15
- b.eq 2f
+ // ARM MPIDR_EL1 bytes: Aff3 (AArch64), Stuff, Aff2, Aff1, Aff0
+ // Test the the MPIDR_EL1 register against 0xff00ffffff to
+ // extract the primary CPU.
+ ldr x1, =0xff00ffffff
+ tst x4, x1 // check for cpuid==zero
+ mov x1, xzr // load previous 'xzr' value back to x1
+ b.eq 2f // secondary CPU
/*
* Secondary CPUs