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authorSteve Reinhardt <stever@eecs.umich.edu>2003-11-03 20:35:05 -0800
committerSteve Reinhardt <stever@eecs.umich.edu>2003-11-03 20:35:05 -0800
commite4b52476bc00fe8c0115ee5ec6e9551447cb04a3 (patch)
tree0671e5be86419c60743915af2f3503fa6de28ac4 /arch/alpha/isa_desc
parent02795babaf52cbf6f8c29bbb2aecfc0e60b46b63 (diff)
parent29474bdf027fe3396e0be2f6acbe2a6b89136bc2 (diff)
downloadgem5-e4b52476bc00fe8c0115ee5ec6e9551447cb04a3.tar.xz
Automerge
--HG-- extra : convert_revision : 2ca18ecbf04a1de72391073d0a5309fdbbdfefda
Diffstat (limited to 'arch/alpha/isa_desc')
-rw-r--r--arch/alpha/isa_desc36
1 files changed, 25 insertions, 11 deletions
diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc
index 6c2888685..e3b8cf01b 100644
--- a/arch/alpha/isa_desc
+++ b/arch/alpha/isa_desc
@@ -28,10 +28,11 @@ let {{
#include "cpu/simple_cpu/simple_cpu.hh"
#include "cpu/static_inst.hh"
#include "sim/annotation.hh"
-#include "sim/sim_events.hh"
+#include "sim/sim_exit.hh"
#ifdef FULL_SYSTEM
-#include "targetarch/ev5.hh"
+#include "arch/alpha/ev5.hh"
+#include "arch/alpha/pseudo_inst.hh"
#endif
namespace AlphaISA;
@@ -2372,7 +2373,7 @@ decode OPCODE default Unknown::unknown() {
format EmulatedCallPal {
0x00: halt ({{
if (!xc->misspeculating())
- SimExit("halt instruction encountered");
+ SimExit(curTick, "halt instruction encountered");
}});
0x83: callsys({{
if (!xc->misspeculating())
@@ -2417,11 +2418,8 @@ decode OPCODE default Unknown::unknown() {
}
}});
0x01: quiesce({{
- if (!xc->misspeculating()) {
- Annotate::QUIESCE(xc);
- xc->setStatus(ExecContext::Suspended);
- xc->kernelStats.quiesce();
- }
+ if (!xc->misspeculating())
+ AlphaPseudo::quiesce(xc);
}});
0x10: ivlb({{
if (!xc->misspeculating()) {
@@ -2433,14 +2431,30 @@ decode OPCODE default Unknown::unknown() {
if (!xc->misspeculating())
Annotate::EndInterval(xc);
}}, No_OpClass);
- 0x20: m5exit({{
+ 0x20: m5exit_old({{
if (!xc->misspeculating())
- SimExit("m5_exit instruction encountered");
+ AlphaPseudo::m5exit_old(xc);
+ }}, No_OpClass);
+ 0x21: m5exit({{
+ if (!xc->misspeculating())
+ AlphaPseudo::m5exit(xc);
}}, No_OpClass);
0x30: initparam({{ Ra = xc->cpu->system->init_param; }});
0x40: resetstats({{
if (!xc->misspeculating())
- Statistics::reset();
+ AlphaPseudo::resetstats(xc);
+ }});
+ 0x41: dumpstats({{
+ if (!xc->misspeculating())
+ AlphaPseudo::dumpstats(xc);
+ }});
+ 0x42: dumpresetstats({{
+ if (!xc->misspeculating())
+ AlphaPseudo::dumpresetstats(xc);
+ }});
+ 0x43: m5checkpoint({{
+ if (!xc->misspeculating())
+ AlphaPseudo::m5checkpoint(xc);
}});
}
}