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author | Andrew Schultz <alschult@umich.edu> | 2004-06-02 13:57:08 -0400 |
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committer | Andrew Schultz <alschult@umich.edu> | 2004-06-02 13:57:08 -0400 |
commit | 44a2a2336e7f0d2048d3e79cbabf2e081abc0916 (patch) | |
tree | fc131828f019263e447838e9083f87d82bcb0df3 /arch/isa_parser.py | |
parent | 08b7d261b2703ff5d00f39ab80845dc6d4c90f57 (diff) | |
parent | f89043293faf336cd7270ecb6d96bfbb9bdcce4b (diff) | |
download | gem5-44a2a2336e7f0d2048d3e79cbabf2e081abc0916.tar.xz |
Merge zizzer:/bk/linux
into zower.eecs.umich.edu:/z/alschult/DiskModel/linux
--HG--
extra : convert_revision : 2b4893331f15b07c7f83148f6271d8ced0fcd6be
Diffstat (limited to 'arch/isa_parser.py')
-rwxr-xr-x | arch/isa_parser.py | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/isa_parser.py b/arch/isa_parser.py index c808c2565..011ce7623 100755 --- a/arch/isa_parser.py +++ b/arch/isa_parser.py @@ -1493,19 +1493,19 @@ class CodeBlock: # These are good enough for most cases, and will be overridden # later otherwise. if 'IsStore' in self.flags: - self.op_class = 'WrPort' + self.op_class = 'MemWriteOp' elif 'IsLoad' in self.flags or 'IsPrefetch' in self.flags: - self.op_class = 'RdPort' + self.op_class = 'MemReadOp' elif 'IsFloating' in self.flags: - self.op_class = 'FloatADD' + self.op_class = 'FloatAddOp' else: - self.op_class = 'IntALU' + self.op_class = 'IntAluOp' # Assume all instruction flags are of the form 'IsFoo' instFlagRE = re.compile(r'Is.*') -# OpClass constants are just a little more complicated -opClassRE = re.compile(r'Int.*|Float.*|.*Port|No_OpClass') +# OpClass constants end in 'Op' except No_OpClass +opClassRE = re.compile(r'.*Op|No_OpClass') class InstObjParams: def __init__(self, mnem, class_name, base_class = '', |