Merged head into linux tree

base/stats/mysql.hh:
    Rename of Statsistics namespace to stats... merge from head

--HG--
extra : convert_revision : a5a7f6268b35e75fba1b1800a74fcd6dbd09d974

6 files changed, 155 insertions, 111 deletions

diff --git a/arch/alpha/alpha_memory.cc b/arch/alpha/alpha_memory.cc
index 1a1c738ec..31f5a9b20 100644
--- a/arch/alpha/alpha_memory.cc
+++ b/arch/alpha/alpha_memory.cc
@@ -440,8 +440,8 @@ AlphaDTB::fault(Addr vaddr, uint64_t flags, ExecContext *xc) const
         ipr[AlphaISA::IPR_VA] = vaddr;
 
         // set MM_STAT register flags
-        ipr[AlphaISA::IPR_MM_STAT] = (((xc->regs.opcode & 0x3f) << 11)
-                               | ((xc->regs.ra & 0x1f) << 6)
+        ipr[AlphaISA::IPR_MM_STAT] = (((OPCODE(xc->getInst()) & 0x3f) << 11)
+                               | ((RA(xc->getInst()) & 0x1f) << 6)
                                | (flags & 0x3f));
 
         // set VA_FORM register with faulting formatted address
diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc
index f037a34ac..ecf66f4f5 100644
--- a/arch/alpha/ev5.cc
+++ b/arch/alpha/ev5.cc
@@ -1,15 +1,15 @@
 /* $Id$ */
 
-#include "targetarch/alpha_memory.hh"
-#ifdef DEBUG
-#include "sim/debug.hh"
-#endif
+#include "arch/alpha/alpha_memory.hh"
+#include "arch/alpha/isa_traits.hh"
+#include "arch/alpha/osfpal.hh"
+#include "base/kgdb.h"
+#include "base/remote_gdb.hh"
+#include "base/stats/events.hh"
 #include "cpu/exec_context.hh"
+#include "cpu/fast_cpu/fast_cpu.hh"
+#include "sim/debug.hh"
 #include "sim/sim_events.hh"
-#include "targetarch/isa_traits.hh"
-#include "base/remote_gdb.hh"
-#include "base/kgdb.h"	// for ALPHA_KENTRY_IF
-#include "targetarch/osfpal.hh"
 
 #ifdef FULL_SYSTEM
 
@@ -99,9 +99,71 @@ AlphaISA::initIPRs(RegFile *regs)
 }
 
 
+template <class XC>
+void
+AlphaISA::processInterrupts(XC *xc)
+{
+    //Check if there are any outstanding interrupts
+    //Handle the interrupts
+    int ipl = 0;
+    int summary = 0;
+    IntReg *ipr = xc->getIprPtr();
+
+    check_interrupts = 0;
+
+    if (ipr[IPR_ASTRR])
+        panic("asynchronous traps not implemented\n");
+
+    if (ipr[IPR_SIRR]) {
+        for (int i = INTLEVEL_SOFTWARE_MIN;
+             i < INTLEVEL_SOFTWARE_MAX; i++) {
+            if (ipr[IPR_SIRR] & (ULL(1) << i)) {
+                // See table 4-19 of the 21164 hardware reference
+                ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
+                summary |= (ULL(1) << i);
+            }
+        }
+    }
+
+    uint64_t interrupts = xc->intr_status();
+
+    if (interrupts) {
+        for (int i = INTLEVEL_EXTERNAL_MIN;
+             i < INTLEVEL_EXTERNAL_MAX; i++) {
+            if (interrupts & (ULL(1) << i)) {
+                // See table 4-19 of the 21164 hardware reference
+                ipl = i;
+                summary |= (ULL(1) << i);
+            }
+        }
+    }
+
+    if (ipl && ipl > ipr[IPR_IPLR]) {
+        ipr[IPR_ISR] = summary;
+        ipr[IPR_INTID] = ipl;
+        xc->trap(Interrupt_Fault);
+        DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
+                ipr[IPR_IPLR], ipl, summary);
+    }
+
+}
+
+template <class XC>
+void
+AlphaISA::zeroRegisters(XC *xc)
+{
+    // Insure ISA semantics
+    // (no longer very clean due to the change in setIntReg() in the
+    // cpu model.  Consider changing later.)
+    xc->xc->setIntReg(ZeroReg, 0);
+    xc->xc->setFloatRegDouble(ZeroReg, 0.0);
+}
+
 void
 ExecContext::ev5_trap(Fault fault)
 {
+    Stats::recordEvent(csprintf("Fault %s", FaultName(fault)));
+
     assert(!misspeculating());
     kernelStats.fault(fault);
 
@@ -581,4 +643,12 @@ ExecContext::simPalCheck(int palFunc)
     return true;
 }
 
+//Forward instantiation for FastCPU object
+template
+void AlphaISA::processInterrupts(FastCPU *xc);
+
+//Forward instantiation for FastCPU object
+template
+void AlphaISA::zeroRegisters(FastCPU *xc);
+
 #endif // FULL_SYSTEM
diff --git a/arch/alpha/ev5.hh b/arch/alpha/ev5.hh
index 636e37adb..517e1111f 100644
--- a/arch/alpha/ev5.hh
+++ b/arch/alpha/ev5.hh
@@ -75,6 +75,8 @@
 #define MM_STAT_ACV_MASK		0x0002
 #define MM_STAT_WR_MASK			0x0001
 
+#define OPCODE(X)                       (X >> 26) & 0x3f
+#define RA(X)                           (X >> 21) & 0x1f
 
 ////////////////////////////////////////////////////////////////////////
 //
diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc
index f964101df..8641c2880 100644
--- a/arch/alpha/isa_desc
+++ b/arch/alpha/isa_desc
@@ -1374,8 +1374,8 @@ output decoder {{
     }
 }};
 
-def format EmulatedCallPal(code) {{
-    iop = InstObjParams(name, Name, 'EmulatedCallPal', CodeBlock(code))
+def format EmulatedCallPal(code, *flags) {{
+    iop = InstObjParams(name, Name, 'EmulatedCallPal', CodeBlock(code), flags)
     header_output = BasicDeclare.subst(iop)
     decoder_output = BasicConstructor.subst(iop)
     decode_block = BasicDecode.subst(iop)
@@ -1436,8 +1436,8 @@ output decoder {{
     }
 }};
 
-def format CallPal(code) {{
-    iop = InstObjParams(name, Name, 'CallPalBase', CodeBlock(code))
+def format CallPal(code, *flags) {{
+    iop = InstObjParams(name, Name, 'CallPalBase', CodeBlock(code), flags)
     header_output = BasicDeclare.subst(iop)
     decoder_output = BasicConstructor.subst(iop)
     decode_block = BasicDecode.subst(iop)
@@ -1588,6 +1588,9 @@ output header {{
 	FailUnimplemented(const char *_mnemonic, MachInst _machInst)
 	    : AlphaStaticInst(_mnemonic, _machInst, No_OpClass)
 	{
+	    // don't call execute() (which panics) if we're on a
+	    // speculative path
+	    flags[IsNonSpeculative] = true;
 	}
 
 	%(BasicExecDeclare)s
@@ -1615,6 +1618,9 @@ output header {{
 	WarnUnimplemented(const char *_mnemonic, MachInst _machInst)
 	    : AlphaStaticInst(_mnemonic, _machInst, No_OpClass), warned(false)
 	{
+	    // don't call execute() (which panics) if we're on a
+	    // speculative path
+	    flags[IsNonSpeculative] = true;
 	}
 
 	%(BasicExecDeclare)s
@@ -1646,9 +1652,8 @@ output exec {{
     FailUnimplemented::execute(%(CPU_exec_context)s *xc,
 			       Trace::InstRecord *traceData)
     {
-	if (!xc->misspeculating())
-	    panic("attempt to execute unimplemented instruction '%s' "
-		  "(inst 0x%08x, opcode 0x%x)", mnemonic, machInst, OPCODE);
+	panic("attempt to execute unimplemented instruction '%s' "
+	      "(inst 0x%08x, opcode 0x%x)", mnemonic, machInst, OPCODE);
 	return Unimplemented_Opcode_Fault;
     }
 
@@ -1656,42 +1661,24 @@ output exec {{
     WarnUnimplemented::execute(%(CPU_exec_context)s *xc,
 			       Trace::InstRecord *traceData)
     {
-	if (!xc->misspeculating())
-	    if (!warned) {
-		warn("instruction '%s' unimplemented\n", mnemonic);
-		warned = true;
-	    }
+	if (!warned) {
+	    warn("instruction '%s' unimplemented\n", mnemonic);
+	    warned = true;
+	}
 
 	return No_Fault;
     }
 }};
 
 
-def template WarnUnimplDeclare {{
-    /**
-     * Static instruction class for "%(mnemonic)s".
-     */
-    class %(class_name)s : public %(base_class)s
-    {
-      public:
-	/// Constructor
-	%(class_name)s(MachInst machInst)
-	     : %(base_class)s("%(mnemonic)s", machInst)
-	{
-	}
-    };
-}};
-
-
 def format FailUnimpl() {{
     iop = InstObjParams(name, 'FailUnimplemented')
     decode_block = BasicDecodeWithMnemonic.subst(iop)
 }};
 
 def format WarnUnimpl() {{
-    iop = InstObjParams(name, Name, 'WarnUnimplemented')
-    header_output = WarnUnimplDeclare.subst(iop)
-    decode_block = BasicDecode.subst(iop)
+    iop = InstObjParams(name, 'WarnUnimplemented')
+    decode_block = BasicDecodeWithMnemonic.subst(iop)
 }};
 
 output header {{
@@ -1707,6 +1694,9 @@ output header {{
 	Unknown(MachInst _machInst)
 	    : AlphaStaticInst("unknown", _machInst, No_OpClass)
 	{
+	    // don't call execute() (which panics) if we're on a
+	    // speculative path
+	    flags[IsNonSpeculative] = true;
 	}
 
 	%(BasicExecDeclare)s
@@ -1733,9 +1723,8 @@ output exec {{
     Fault
     Unknown::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData)
     {
-	if (!xc->misspeculating())
-	    panic("attempt to execute unknown instruction "
-		  "(inst 0x%08x, opcode 0x%x)", machInst, OPCODE);
+	panic("attempt to execute unknown instruction "
+	      "(inst 0x%08x, opcode 0x%x)", machInst, OPCODE);
 	return Unimplemented_Opcode_Fault;
     }
 }};
@@ -2420,16 +2409,12 @@ decode OPCODE default Unknown::unknown() {
 	format BasicOperate {
 	    0xe000: rc({{
 		Ra = xc->readIntrFlag();
-		if (!xc->misspeculating()) {
-		    xc->setIntrFlag(0);
-		}
-	    }});
+		xc->setIntrFlag(0);
+	    }}, IsNonSpeculative);
 	    0xf000: rs({{
 		Ra = xc->readIntrFlag();
-		if (!xc->misspeculating()) {
-		    xc->setIntrFlag(1);
-		}
-	    }});
+		xc->setIntrFlag(1);
+	    }}, IsNonSpeculative);
 	}
 #else
 	format FailUnimpl {
@@ -2449,38 +2434,26 @@ decode OPCODE default Unknown::unknown() {
 	    fault = Unimplemented_Opcode_Fault;
 	}
 	else {
-	    bool dopal = true;
-
-	    if (!xc->misspeculating()) {
-		// check to see if simulator wants to do something special
-		// on this PAL call (including maybe suppress it)
-		dopal = xc->simPalCheck(palFunc);
-
-		if (dopal) {
-		    AlphaISA::swap_palshadow(&xc->xcBase()->regs, true);
-		    xc->setIpr(AlphaISA::IPR_EXC_ADDR, NPC);
-		}
-	    }
+	    // check to see if simulator wants to do something special
+	    // on this PAL call (including maybe suppress it)
+	    bool dopal = xc->simPalCheck(palFunc);
 
-	    // if we're misspeculating, it's still safe (if
-	    // unrealistic) to set NPC, as the control-flow change
-	    // won't get committed.
 	    if (dopal) {
+		AlphaISA::swap_palshadow(&xc->xcBase()->regs, true);
+		xc->setIpr(AlphaISA::IPR_EXC_ADDR, NPC);
 		NPC = xc->readIpr(AlphaISA::IPR_PAL_BASE, fault) + palOffset;
 	    }
 	}
-    }});
+    }}, IsNonSpeculative);
 #else
     0x00: decode PALFUNC {
 	format EmulatedCallPal {
 	    0x00: halt ({{
-		if (!xc->misspeculating()) 
-		    SimExit(curTick, "halt instruction encountered");
-	    }});
+		SimExit(curTick, "halt instruction encountered");
+	    }}, IsNonSpeculative);
 	    0x83: callsys({{ 
-		if (!xc->misspeculating()) 
-		    xc->syscall();
-	    }});
+		xc->syscall();
+	    }}, IsNonSpeculative);
 	    // Read uniq reg into ABI return value register (r0)
 	    0x9e: rduniq({{ R0 = Runiq; }});
 	    // Write uniq reg with value from ABI arg register (r16)
@@ -2514,46 +2487,36 @@ decode OPCODE default Unknown::unknown() {
 	// M5 special opcodes use the reserved 0x01 opcode space
 	0x01: decode M5FUNC {
 	    0x00: arm({{
-		if (!xc->misspeculating())
-		    AlphaPseudo::arm(xc->xcBase());
-	    }});
+		AlphaPseudo::arm(xc->xcBase());
+	    }}, IsNonSpeculative);
 	    0x01: quiesce({{
-		if (!xc->misspeculating())
-		    AlphaPseudo::quiesce(xc->xcBase());
-	    }});
+		AlphaPseudo::quiesce(xc->xcBase());
+	    }}, IsNonSpeculative);
 	    0x10: ivlb({{
-		if (!xc->misspeculating())
-		    AlphaPseudo::ivlb(xc->xcBase());
-	    }}, No_OpClass);
+		AlphaPseudo::ivlb(xc->xcBase());
+	    }}, No_OpClass, IsNonSpeculative);
 	    0x11: ivle({{
-		if (!xc->misspeculating())
-		    AlphaPseudo::ivle(xc->xcBase());
-	    }}, No_OpClass);
+		AlphaPseudo::ivle(xc->xcBase());
+	    }}, No_OpClass, IsNonSpeculative);
 	    0x20: m5exit_old({{
-		if (!xc->misspeculating())
-		    AlphaPseudo::m5exit_old(xc->xcBase());
-	    }}, No_OpClass);
+		AlphaPseudo::m5exit_old(xc->xcBase());
+	    }}, No_OpClass, IsNonSpeculative);
 	    0x21: m5exit({{
-		if (!xc->misspeculating())
-		    AlphaPseudo::m5exit(xc->xcBase());
-	    }}, No_OpClass);
+		AlphaPseudo::m5exit(xc->xcBase());
+	    }}, No_OpClass, IsNonSpeculative);
             0x30: initparam({{ Ra = xc->xcBase()->cpu->system->init_param; }});
             0x40: resetstats({{
-		if (!xc->misspeculating())
-		    AlphaPseudo::resetstats(xc->xcBase());
-	    }});
+		AlphaPseudo::resetstats(xc->xcBase());
+	    }}, IsNonSpeculative);
             0x41: dumpstats({{
-		if (!xc->misspeculating())
-		    AlphaPseudo::dumpstats(xc->xcBase());
-	    }});
+		AlphaPseudo::dumpstats(xc->xcBase());
+	    }}, IsNonSpeculative);
             0x42: dumpresetstats({{
-		if (!xc->misspeculating())
-		    AlphaPseudo::dumpresetstats(xc->xcBase());
-	    }});
+		AlphaPseudo::dumpresetstats(xc->xcBase());
+	    }}, IsNonSpeculative);
             0x43: m5checkpoint({{
-		if (!xc->misspeculating())
-		    AlphaPseudo::m5checkpoint(xc->xcBase());
-	    }});
+		AlphaPseudo::m5checkpoint(xc->xcBase());
+	    }}, IsNonSpeculative);
 	}
     }
 
diff --git a/arch/alpha/isa_traits.hh b/arch/alpha/isa_traits.hh
index 05ab89978..37ba77192 100644
--- a/arch/alpha/isa_traits.hh
+++ b/arch/alpha/isa_traits.hh
@@ -33,6 +33,7 @@
 #include "targetarch/faults.hh"
 #include "base/misc.hh"
 
+class FastCPU;
 class FullCPU;
 class Checkpoint;
 
@@ -156,8 +157,6 @@ class AlphaISA
         int intrflag;			// interrupt flag
         bool pal_shadow;		// using pal_shadow registers
 #endif // FULL_SYSTEM
-        // Are these architectural, or just for convenience?
-        uint8_t opcode, ra;		// current instruction details (for intr's)
 
         void serialize(std::ostream &os);
         void unserialize(Checkpoint *cp, const std::string &section);
@@ -233,6 +232,13 @@ class AlphaISA
                                        ConfigNode *node,
                                        RegFile &regs);
 #endif
+
+    /**
+     * Function to insure ISA semantics about 0 registers.
+     * @param xc The execution context.
+     */
+    template <class XC>
+    static void zeroRegisters(XC *xc);
 };
 
 
diff --git a/arch/isa_parser.py b/arch/isa_parser.py
index 621720709..c808c2565 100755
--- a/arch/isa_parser.py
+++ b/arch/isa_parser.py
@@ -630,6 +630,9 @@ class CpuModel:
 CpuModel('SimpleCPU', 'simple_cpu_exec.cc',
          '#include "cpu/simple_cpu/simple_cpu.hh"',
          { 'CPU_exec_context': 'SimpleCPU' })
+CpuModel('FastCPU', 'fast_cpu_exec.cc',
+         '#include "cpu/fast_cpu/fast_cpu.hh"',
+         { 'CPU_exec_context': 'FastCPU' })
 CpuModel('FullCPU', 'full_cpu_exec.cc',
          '#include "cpu/full_cpu/dyn_inst.hh"',
          { 'CPU_exec_context': 'DynInst' })
@@ -1057,10 +1060,10 @@ class IntRegOperandTraits(OperandTraits):
         if (type == 'float' or type == 'double'):
             error(0, 'Attempt to read integer register as FP')
         if (size == self.dflt_size):
-            return '%s = xc->readIntReg(_srcRegIdx[%d]);\n' % \
+            return '%s = xc->readIntReg(this, %d);\n' % \
                    (op_desc.munged_name, op_desc.src_reg_idx)
         else:
-            return '%s = bits(xc->readIntReg(_srcRegIdx[%d]), %d, 0);\n' % \
+            return '%s = bits(xc->readIntReg(this, %d), %d, 0);\n' % \
                    (op_desc.munged_name, op_desc.src_reg_idx, size-1)
 
     def makeWrite(self, op_desc):
@@ -1074,7 +1077,7 @@ class IntRegOperandTraits(OperandTraits):
         wb = '''
         {
             %s final_val = %s;
-            xc->setIntReg(_destRegIdx[%d], final_val);\n
+            xc->setIntReg(this, %d, final_val);\n
             if (traceData) { traceData->setData(final_val); }
         }''' % (self.dflt_type, final_val, op_desc.dest_reg_idx)
         return wb
@@ -1107,7 +1110,7 @@ class FloatRegOperandTraits(OperandTraits):
             func = 'readFloatRegInt'
             if (size != self.dflt_size):
                 bit_select = 1
-        base = 'xc->%s(_srcRegIdx[%d] - FP_Base_DepTag)' % \
+        base = 'xc->%s(this, %d)' % \
                (func, op_desc.src_reg_idx)
         if bit_select:
             return '%s = bits(%s, %d, 0);\n' % \
@@ -1130,7 +1133,7 @@ class FloatRegOperandTraits(OperandTraits):
         wb = '''
         {
             %s final_val = %s;
-            xc->%s(_destRegIdx[%d] - FP_Base_DepTag, final_val);\n
+            xc->%s(this, %d, final_val);\n
             if (traceData) { traceData->setData(final_val); }
         }''' % (type, final_val, func, op_desc.dest_reg_idx)
         return wb