merge with m5 head

--HG--
extra : convert_revision : c90339248d1ee74df1c6b90a77ec9ea41f646311

4 files changed, 80 insertions, 8 deletions

diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc
index 8494ee9f6..551cbdabf 100644
--- a/arch/alpha/ev5.cc
+++ b/arch/alpha/ev5.cc
@@ -237,10 +237,17 @@ ExecContext::readIpr(int idx, Fault &fault)
         retval = ipr[idx];
         break;
 
+      case AlphaISA::IPR_CC:
+        retval |= ipr[idx] & ULL(0xffffffff00000000);
+        retval |= curTick  & ULL(0x00000000ffffffff);
+        break;
+
       case AlphaISA::IPR_VA:
         // SFX: unlocks interrupt status registers
         retval = ipr[idx];
-        regs.intrlock = false;
+
+        if (!misspeculating())
+            regs.intrlock = false;
         break;
 
       case AlphaISA::IPR_VA_FORM:
@@ -253,7 +260,7 @@ ExecContext::readIpr(int idx, Fault &fault)
 
       case AlphaISA::IPR_DTB_PTE:
         {
-            AlphaISA::PTE &pte = dtb->index();
+            AlphaISA::PTE &pte = dtb->index(!misspeculating());
 
             retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
             retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
@@ -327,13 +334,25 @@ ExecContext::setIpr(int idx, uint64_t val)
       case AlphaISA::IPR_PAL_BASE:
       case AlphaISA::IPR_IC_PERR_STAT:
       case AlphaISA::IPR_DC_PERR_STAT:
-      case AlphaISA::IPR_CC_CTL:
-      case AlphaISA::IPR_CC:
       case AlphaISA::IPR_PMCTR:
         // write entire quad w/ no side-effect
         ipr[idx] = val;
         break;
 
+      case AlphaISA::IPR_CC_CTL:
+        // This IPR resets the cycle counter.  We assume this only
+        // happens once... let's verify that.
+        assert(ipr[idx] == 0);
+        ipr[idx] = 1;
+        break;
+
+      case AlphaISA::IPR_CC:
+        // This IPR only writes the upper 64 bits.  It's ok to write
+        // all 64 here since we mask out the lower 32 in rpcc (see
+        // isa_desc).
+        ipr[idx] = val;
+        break;
+
       case AlphaISA::IPR_PALtemp23:
         // write entire quad w/ no side-effect
         ipr[idx] = val;
diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc
index 75b2f4138..0da087f97 100644
--- a/arch/alpha/isa_desc
+++ b/arch/alpha/isa_desc
@@ -5,7 +5,7 @@
 
 let {{
     global rcs_id
-    rcs_id = "$Id$"
+    rcs_id = "$Id: s.isa_desc 1.43 04/02/29 22:41:10-05:00 ehallnor@zazzer.eecs.umich.edu $"
 }};
 
 
@@ -1000,10 +1000,50 @@ def template PrefetchDeclare {{
      */
     class %(class_name)s : public %(base_class)s
     {
+      protected:
+
+	/**
+	 * "Fake" effective address computation class for "%(mnemonic)s".
+	 */
+	class EAComp : public EACompBase
+	{
+	  public:
+	    /// Constructor
+	    EAComp(MachInst machInst)
+		: EACompBase(machInst)
+	    {
+		%(ea_constructor)s;
+	    }
+	};
+
+	/**
+	 * "Fake" memory access instruction class for "%(mnemonic)s".
+	 */
+	class MemAcc : public MemAccBase
+	{
+	  public:
+	    /// Constructor
+	    MemAcc(MachInst machInst)
+		: MemAccBase(machInst, %(op_class)s)
+	    {
+		%(memacc_constructor)s;
+	    }
+	};
+
+	/// Pointer to EAComp object.
+	StaticInstPtr<AlphaISA> eaCompPtr;
+	/// Pointer to MemAcc object.
+	StaticInstPtr<AlphaISA> memAccPtr;
+
       public:
+
+	StaticInstPtr<AlphaISA> eaCompInst() { return eaCompPtr; }
+	StaticInstPtr<AlphaISA> memAccInst() { return memAccPtr; }
+
 	/// Constructor
 	%(class_name)s(MachInst machInst)
-	     : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
+	     : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s),
+	       eaCompPtr(new EAComp(machInst)), memAccPtr(new MemAcc(machInst))
 	{
 	    %(constructor)s;
 	}
@@ -1814,6 +1854,9 @@ decode OPCODE default Unknown::unknown() {
 	0x23: ldt({{ EA = Rb + disp; }}, {{ Fa = Mem.df; }});
 	0x2a: ldl_l({{ EA = Rb + disp; }}, {{ Ra.sl = Mem.sl; }}, LOCKED);
 	0x2b: ldq_l({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.uq; }}, LOCKED);
+	0x20: copy_load({{EA = Ra;}}, 
+	                {{ fault = memAccessObj->copySrcTranslate(EA);}},
+			IsMemRef, IsLoad, IsCopy);
     }
 
     format LoadOrPrefetch {
@@ -1833,6 +1876,9 @@ decode OPCODE default Unknown::unknown() {
 	0x0f: stq_u({{ EA = (Rb + disp) & ~7; }}, {{ Mem.uq = Ra.uq; }});
 	0x26: sts({{ EA = Rb + disp; }}, {{ Mem.ul = t_to_s(Fa.uq); }});
 	0x27: stt({{ EA = Rb + disp; }}, {{ Mem.df = Fa; }});
+	0x24: copy_store({{EA = Rb;}},
+	                 {{ fault = memAccessObj->copy(EA);}},
+			 IsMemRef, IsStore, IsCopy);
     }
 
     format StoreCond {
@@ -2342,7 +2388,13 @@ decode OPCODE default Unknown::unknown() {
 	}
 
 	format BasicOperate {
-	    0xc000: rpcc({{ Ra = curTick; }});
+	    0xc000: rpcc({{
+#ifdef FULL_SYSTEM
+		Ra = xc->readIpr(AlphaISA::IPR_CC, fault);
+#else
+		Ra = curTick;
+#endif
+	    }});
 
 	    // All of the barrier instructions below do nothing in
 	    // their execute() methods (hence the empty code blocks).
diff --git a/arch/alpha/osfpal.cc b/arch/alpha/osfpal.cc
index 4c0ace8c0..90d645ef1 100644
--- a/arch/alpha/osfpal.cc
+++ b/arch/alpha/osfpal.cc
@@ -224,8 +224,8 @@ namespace {
         0,		// 0xbc
         0,		// 0xbd
         "nphalt",	// 0xbe
+        "copypal",	// 0xbf
 #if 0
-        0,		// 0xbf
         0,		// 0xc0
         0,		// 0xc1
         0,		// 0xc2
diff --git a/arch/alpha/osfpal.hh b/arch/alpha/osfpal.hh
index 61e545306..419235b4a 100644
--- a/arch/alpha/osfpal.hh
+++ b/arch/alpha/osfpal.hh
@@ -70,6 +70,7 @@ struct PAL
         gentrap = 0xaa,
         clrfen = 0xae,
         nphalt = 0xbe,
+        copypal = 0xbf,
         NumCodes
     };