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| author | Nilay Vaish <nilay@cs.wisc.edu> | 2012-03-01 11:37:02 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2012-03-01 11:37:02 -0600 |
| commit | c80af04d7df7586352841a65a4398baf21e0c122 (patch) | |
| tree | 60292236eecafe541bc47bb9b987e6fb7d067dae /configs/common | |
| parent | e11847bfa949481322f2031049402a093ed442a7 (diff) | |
| download | gem5-c80af04d7df7586352841a65a4398baf21e0c122.tar.xz | |
x86: Fix switching of CPUs
This patch prevents creation of interrupt controller for
cpus that will be switched in later
Diffstat (limited to 'configs/common')
| -rw-r--r-- | configs/common/CacheConfig.py | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py index b9192fcbf..009cb1bf6 100644 --- a/configs/common/CacheConfig.py +++ b/configs/common/CacheConfig.py @@ -70,6 +70,7 @@ def config_cache(options, system): PageTableWalkerCache()) else: system.cpu[i].addPrivateSplitL1Caches(icache, dcache) + system.cpu[i].createInterruptController() if options.l2cache: system.cpu[i].connectAllPorts(system.tol2bus, system.membus) else: |