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| author | Nilay Vaish <nilay@cs.wisc.edu> | 2014-03-20 09:14:14 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2014-03-20 09:14:14 -0500 |
| commit | b5cc4c760478240bf8c5f7de977bf2b56fd8dfd4 (patch) | |
| tree | f4d9bf0eee60c59b294f8e25504e67e58bfdd1f6 /configs/example/fs.py | |
| parent | f2059f8399b22ecc544413a0e9d5a13a6f965411 (diff) | |
| download | gem5-b5cc4c760478240bf8c5f7de977bf2b56fd8dfd4.tar.xz | |
config: ruby: rename _cpu_ruby_ports to _cpu_ports
Diffstat (limited to 'configs/example/fs.py')
| -rw-r--r-- | configs/example/fs.py | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/configs/example/fs.py b/configs/example/fs.py index 6c71ef432..584748299 100644 --- a/configs/example/fs.py +++ b/configs/example/fs.py @@ -149,18 +149,18 @@ def build_test_system(np): cpu.createThreads() cpu.createInterruptController() - cpu.icache_port = test_sys.ruby._cpu_ruby_ports[i].slave - cpu.dcache_port = test_sys.ruby._cpu_ruby_ports[i].slave + cpu.icache_port = test_sys.ruby._cpu_ports[i].slave + cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave if buildEnv['TARGET_ISA'] == "x86": - cpu.itb.walker.port = test_sys.ruby._cpu_ruby_ports[i].slave - cpu.dtb.walker.port = test_sys.ruby._cpu_ruby_ports[i].slave + cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave + cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave - cpu.interrupts.pio = test_sys.ruby._cpu_ruby_ports[i].master - cpu.interrupts.int_master = test_sys.ruby._cpu_ruby_ports[i].slave - cpu.interrupts.int_slave = test_sys.ruby._cpu_ruby_ports[i].master + cpu.interrupts.pio = test_sys.ruby._cpu_ports[i].master + cpu.interrupts.int_master = test_sys.ruby._cpu_ports[i].slave + cpu.interrupts.int_slave = test_sys.ruby._cpu_ports[i].master - test_sys.ruby._cpu_ruby_ports[i].access_phys_mem = True + test_sys.ruby._cpu_ports[i].access_phys_mem = True # Create the appropriate memory controllers # and connect them to the IO bus |