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authorGedare Bloom <gedare@gwmail.gwu.edu>2011-06-17 12:20:10 -0500
committerGedare Bloom <gedare@gwmail.gwu.edu>2011-06-17 12:20:10 -0500
commit3f1f16703d7d7fafb29fb47415b9aa959fb8eda7 (patch)
treebd3d9493221af378095342a3f8c219fd69739499 /configs/example
parent8b4307f8d863b1805ec0e282bccda23ff4863f16 (diff)
downloadgem5-3f1f16703d7d7fafb29fb47415b9aa959fb8eda7.tar.xz
ARM: Add m5ops and related support for workbegin() and workend() to ARM ISA.
Diffstat (limited to 'configs/example')
-rw-r--r--configs/example/fs.py1
1 files changed, 1 insertions, 0 deletions
diff --git a/configs/example/fs.py b/configs/example/fs.py
index 420cf1f8b..b8f50fc90 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -137,6 +137,7 @@ elif buildEnv['TARGET_ISA'] == "arm":
test_sys = makeArmSystem(test_mem_mode,
options.machine_type, bm[0],
bare_metal=options.bare_metal)
+ setWorkCountOptions(test_sys, options)
else:
fatal("incapable of building non-alpha or non-sparc full system!")