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authorAli Saidi <saidi@eecs.umich.edu>2007-09-05 14:57:50 -0400
committerAli Saidi <saidi@eecs.umich.edu>2007-09-05 14:57:50 -0400
commitdd6a21190e33f6d09ee6ff5ed045f92000c5e801 (patch)
treefdc068f0b01a8551faf63248bc9b6370af2c4ff8 /configs/example
parent57da0594157058f9d741dd19a4f08830652789f3 (diff)
downloadgem5-dd6a21190e33f6d09ee6ff5ed045f92000c5e801.tar.xz
Configuration: Fix example script to only create one L2 if --l2cache and -nX are given as parameters.
Patch submitted by: Jonas Diemer [diemer (a) ida.ing.tu-bs.de] --HG-- extra : convert_revision : 1dfc548d2bc33d622d829bbf385f4bf9700711cd
Diffstat (limited to 'configs/example')
-rw-r--r--configs/example/se.py10
1 files changed, 6 insertions, 4 deletions
diff --git a/configs/example/se.py b/configs/example/se.py
index 639bcd7c6..b4b50a013 100644
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -100,15 +100,17 @@ system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
system.physmem.port = system.membus.port
+if options.l2cache:
+ system.l2 = L2Cache(size='2MB')
+ system.tol2bus = Bus()
+ system.l2.cpu_side = system.tol2bus.port
+ system.l2.mem_side = system.membus.port
+
for i in xrange(np):
if options.caches:
system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
L1Cache(size = '64kB'))
if options.l2cache:
- system.l2 = L2Cache(size='2MB')
- system.tol2bus = Bus()
- system.l2.cpu_side = system.tol2bus.port
- system.l2.mem_side = system.membus.port
system.cpu[i].connectMemPorts(system.tol2bus)
else:
system.cpu[i].connectMemPorts(system.membus)