Hand merge. Stuff probably doesn't compile.

--HG--
rename : arch/alpha/isa_desc => arch/alpha/isa/main.isa
rename : arch/alpha/alpha_linux_process.cc => arch/alpha/linux/process.cc
rename : arch/alpha/alpha_linux_process.hh => arch/alpha/linux/process.hh
rename : arch/alpha/alpha_tru64_process.cc => arch/alpha/tru64/process.cc
rename : arch/alpha/alpha_tru64_process.hh => arch/alpha/tru64/process.hh
rename : cpu/exec_context.cc => cpu/cpu_exec_context.cc
rename : cpu/exec_context.hh => cpu/cpu_exec_context.hh
extra : convert_revision : 7d1efcedd708815d985a951f6f010fbd83dc27e8

30 files changed, 236 insertions, 653 deletions

diff --git a/cpu/o3/2bit_local_pred.hh b/cpu/o3/2bit_local_pred.hh
index a97ce455c..97433e542 100644
--- a/cpu/o3/2bit_local_pred.hh
+++ b/cpu/o3/2bit_local_pred.hh
@@ -30,7 +30,7 @@
 #define __CPU_O3_CPU_2BIT_LOCAL_PRED_HH__
 
 // For Addr type.
-#include "arch/alpha/isa_traits.hh"
+#include "arch/isa_traits.hh"
 #include "cpu/o3/sat_counter.hh"
 
 class DefaultBP
diff --git a/cpu/o3/alpha_cpu.hh b/cpu/o3/alpha_cpu.hh
index cba57d189..0352e9972 100644
--- a/cpu/o3/alpha_cpu.hh
+++ b/cpu/o3/alpha_cpu.hh
@@ -33,12 +33,19 @@
 #define __CPU_O3_CPU_ALPHA_FULL_CPU_HH__
 
 #include "cpu/o3/cpu.hh"
+#include "arch/isa_traits.hh"
+#include "sim/byteswap.hh"
 
 template <class Impl>
 class AlphaFullCPU : public FullO3CPU<Impl>
 {
+  protected:
+    typedef TheISA::IntReg IntReg;
+    typedef TheISA::MiscReg MiscReg;
+    typedef TheISA::RegFile RegFile;
+    typedef TheISA::MiscRegFile MiscRegFile;
+
   public:
-    typedef typename Impl::ISA AlphaISA;
     typedef typename Impl::Params Params;
 
   public:
@@ -85,7 +92,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
         // put the asid in the upper 16 bits of the paddr
         req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16);
         req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16;
-        return No_Fault;
+        return NoFault;
     }
 
     Fault translateInstReq(MemReqPtr &req)
@@ -108,33 +115,24 @@ class AlphaFullCPU : public FullO3CPU<Impl>
     // Later on may want to remove this misc stuff from the regfile and
     // have it handled at this level.  Might prove to be an issue when
     // trying to rename source/destination registers...
-    uint64_t readUniq()
-    {
-        return this->regFile.readUniq();
-    }
-
-    void setUniq(uint64_t val)
+    MiscReg readMiscReg(int misc_reg)
     {
-        this->regFile.setUniq(val);
+        // Dummy function for now.
+        // @todo: Fix this once reg file gets fixed.
+        return 0;
     }
 
-    uint64_t readFpcr()
+    Fault setMiscReg(int misc_reg, const MiscReg &val)
     {
-        return this->regFile.readFpcr();
-    }
-
-    void setFpcr(uint64_t val)
-    {
-        this->regFile.setFpcr(val);
+        // Dummy function for now.
+        // @todo: Fix this once reg file gets fixed.
+        return NoFault;
     }
 
     // Most of the full system code and syscall emulation is not yet
     // implemented.  These functions do show what the final interface will
     // look like.
 #if FULL_SYSTEM
-    uint64_t *getIpr();
-    uint64_t readIpr(int idx, Fault &fault);
-    Fault setIpr(int idx, uint64_t val);
     int readIntrFlag();
     void setIntrFlag(int val);
     Fault hwrei();
@@ -156,13 +154,13 @@ class AlphaFullCPU : public FullO3CPU<Impl>
     // set the register.
     IntReg getSyscallArg(int i)
     {
-        return this->xc->regs.intRegFile[AlphaISA::ArgumentReg0 + i];
+        return this->cpuXC->readIntReg(AlphaISA::ArgumentReg0 + i);
     }
 
     // used to shift args for indirect syscall
     void setSyscallArg(int i, IntReg val)
     {
-        this->xc->regs.intRegFile[AlphaISA::ArgumentReg0 + i] = val;
+        this->cpuXC->setIntReg(AlphaISA::ArgumentReg0 + i, val);
     }
 
     void setSyscallReturn(int64_t return_value)
@@ -173,12 +171,12 @@ class AlphaFullCPU : public FullO3CPU<Impl>
         const int RegA3 = 19;	// only place this is used
         if (return_value >= 0) {
             // no error
-            this->xc->regs.intRegFile[RegA3] = 0;
-            this->xc->regs.intRegFile[AlphaISA::ReturnValueReg] = return_value;
+            this->cpuXC->setIntReg(RegA3, 0);
+            this->cpuXC->setIntReg(AlphaISA::ReturnValueReg, return_value);
         } else {
             // got an error, return details
-            this->xc->regs.intRegFile[RegA3] = (IntReg) -1;
-            this->xc->regs.intRegFile[AlphaISA::ReturnValueReg] = -return_value;
+            this->cpuXC->setIntReg(RegA3, (IntReg) -1);
+            this->cpuXC->setIntReg(AlphaISA::ReturnValueReg, -return_value);
         }
     }
 
@@ -212,9 +210,8 @@ class AlphaFullCPU : public FullO3CPU<Impl>
     {
 #if FULL_SYSTEM && defined(TARGET_ALPHA)
         if (req->flags & LOCKED) {
-            MiscRegFile *cregs = &req->xc->regs.miscRegs;
-            cregs->lock_addr = req->paddr;
-            cregs->lock_flag = true;
+            req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr);
+            req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true);
         }
 #endif
 
@@ -234,32 +231,34 @@ class AlphaFullCPU : public FullO3CPU<Impl>
     Fault write(MemReqPtr &req, T &data)
     {
 #if FULL_SYSTEM && defined(TARGET_ALPHA)
-
-        MiscRegFile *cregs;
+        ExecContext *xc;
 
         // If this is a store conditional, act appropriately
         if (req->flags & LOCKED) {
-            cregs = &this->xc->regs.miscRegs;
+            xc = req->xc;
 
             if (req->flags & UNCACHEABLE) {
                 // Don't update result register (see stq_c in isa_desc)
                 req->result = 2;
-                req->xc->storeCondFailures = 0;//Needed? [RGD]
+                xc->setStCondFailures(0);//Needed? [RGD]
             } else {
-                req->result = cregs->lock_flag;
-                if (!cregs->lock_flag ||
-                    ((cregs->lock_addr & ~0xf) != (req->paddr & ~0xf))) {
-                    cregs->lock_flag = false;
-                    if (((++req->xc->storeCondFailures) % 100000) == 0) {
+                bool lock_flag = xc->readMiscReg(TheISA::Lock_Flag_DepTag);
+                Addr lock_addr = xc->readMiscReg(TheISA::Lock_Addr_DepTag);
+                req->result = lock_flag;
+                if (!lock_flag ||
+                    ((lock_addr & ~0xf) != (req->paddr & ~0xf))) {
+                    xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
+                    xc->setStCondFailures(xc->readStCondFailures() + 1);
+                    if (((xc->readStCondFailures()) % 100000) == 0) {
                         std::cerr << "Warning: "
-                                  << req->xc->storeCondFailures
+                                  << xc->readStCondFailures()
                                   << " consecutive store conditional failures "
-                                  << "on cpu " << this->cpu_id
+                                  << "on cpu " << req->xc->readCpuId()
                                   << std::endl;
                     }
-                    return No_Fault;
+                    return NoFault;
                 }
-                else req->xc->storeCondFailures = 0;
+                else xc->setStCondFailures(0);
             }
         }
 
@@ -269,9 +268,10 @@ class AlphaFullCPU : public FullO3CPU<Impl>
         // Conditionals would have returned above, and wouldn't fall
         // through.
         for (int i = 0; i < this->system->execContexts.size(); i++){
-            cregs = &this->system->execContexts[i]->regs.miscRegs;
-            if ((cregs->lock_addr & ~0xf) == (req->paddr & ~0xf)) {
-                cregs->lock_flag = false;
+            xc = this->system->execContexts[i];
+            if ((xc->readMiscReg(TheISA::Lock_Addr_DepTag) & ~0xf) ==
+                (req->paddr & ~0xf)) {
+                xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
             }
         }
 
diff --git a/cpu/o3/alpha_cpu_builder.cc b/cpu/o3/alpha_cpu_builder.cc
index 3547fb1b5..6025b8ef2 100644
--- a/cpu/o3/alpha_cpu_builder.cc
+++ b/cpu/o3/alpha_cpu_builder.cc
@@ -30,7 +30,6 @@
 #include "base/loader/symtab.hh"
 #include "base/misc.hh"
 #include "cpu/base.hh"
-#include "cpu/exec_context.hh"
 #include "cpu/exetrace.hh"
 #include "cpu/o3/alpha_cpu.hh"
 #include "cpu/o3/alpha_impl.hh"
@@ -50,8 +49,8 @@
 #include "mem/functional/memory_control.hh"
 #include "mem/functional/physical.hh"
 #include "sim/system.hh"
-#include "targetarch/alpha_memory.hh"
-#include "targetarch/vtophys.hh"
+#include "arch/tlb.hh"
+#include "arch/vtophys.hh"
 #else // !FULL_SYSTEM
 #include "mem/functional/functional.hh"
 #endif // FULL_SYSTEM
diff --git a/cpu/o3/alpha_cpu_impl.hh b/cpu/o3/alpha_cpu_impl.hh
index 2a764740b..9f1fa24f6 100644
--- a/cpu/o3/alpha_cpu_impl.hh
+++ b/cpu/o3/alpha_cpu_impl.hh
@@ -26,6 +26,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
+#include "arch/alpha/faults.hh"
 #include "base/cprintf.hh"
 #include "base/statistics.hh"
 #include "base/timebuf.hh"
@@ -42,9 +43,6 @@
 #if FULL_SYSTEM
 #include "arch/alpha/osfpal.hh"
 #include "arch/alpha/isa_traits.hh"
-//#include "arch/alpha/ev5.hh"
-
-//using namespace EV5;
 #endif
 
 template <class Impl>
@@ -168,7 +166,7 @@ AlphaFullCPU<Impl>::copyToXC()
     for (int i = 0; i < AlphaISA::NumIntRegs; ++i)
     {
         renamed_reg = this->renameMap.lookup(i);
-        this->xc->regs.intRegFile[i] = this->regFile.readIntReg(renamed_reg);
+        this->cpuXC->setIntReg(i, this->regFile.readIntReg(renamed_reg));
         DPRINTF(FullCPU, "FullCPU: Copying register %i, has data %lli.\n",
                 renamed_reg, this->regFile.intRegFile[renamed_reg]);
     }
@@ -177,21 +175,27 @@ AlphaFullCPU<Impl>::copyToXC()
     for (int i = 0; i < AlphaISA::NumFloatRegs; ++i)
     {
         renamed_reg = this->renameMap.lookup(i + AlphaISA::FP_Base_DepTag);
-        this->xc->regs.floatRegFile.d[i] =
-            this->regFile.readFloatRegDouble(renamed_reg);
-        this->xc->regs.floatRegFile.q[i] =
-            this->regFile.readFloatRegInt(renamed_reg);
+        this->cpuXC->setFloatRegDouble(i,
+            this->regFile.readFloatRegDouble(renamed_reg));
+        this->cpuXC->setFloatRegInt(i,
+            this->regFile.readFloatRegInt(renamed_reg));
     }
 
-    this->xc->regs.miscRegs.fpcr = this->regFile.miscRegs.fpcr;
-    this->xc->regs.miscRegs.uniq = this->regFile.miscRegs.uniq;
-    this->xc->regs.miscRegs.lock_flag = this->regFile.miscRegs.lock_flag;
-    this->xc->regs.miscRegs.lock_addr = this->regFile.miscRegs.lock_addr;
+    this->cpuXC->setMiscReg(AlphaISA::Fpcr_DepTag,
+                            this->regFile.readMiscReg(AlphaISA::Fpcr_DepTag));
+    this->cpuXC->setMiscReg(AlphaISA::Uniq_DepTag,
+                            this->regFile.readMiscReg(AlphaISA::Uniq_DepTag));
+    this->cpuXC->setMiscReg(AlphaISA::Lock_Flag_DepTag,
+                            this->regFile.readMiscReg(AlphaISA::Lock_Flag_DepTag));
+    this->cpuXC->setMiscReg(AlphaISA::Lock_Addr_DepTag,
+                            this->regFile.readMiscReg(AlphaISA::Lock_Addr_DepTag));
 
-    this->xc->regs.pc = this->rob.readHeadPC();
-    this->xc->regs.npc = this->xc->regs.pc+4;
+    this->cpuXC->setPC(this->rob.readHeadPC());
+    this->cpuXC->setNextPC(this->cpuXC->readPC()+4);
 
-    this->xc->func_exe_inst = this->funcExeInst;
+#if !FULL_SYSTEM
+    this->cpuXC->setFuncExeInst(this->funcExeInst);
+#endif
 }
 
 // This function will probably mess things up unless the ROB is empty and
@@ -210,9 +214,9 @@ AlphaFullCPU<Impl>::copyFromXC()
         DPRINTF(FullCPU, "FullCPU: Copying over register %i, had data %lli, "
                 "now has data %lli.\n",
                 renamed_reg, this->regFile.intRegFile[renamed_reg],
-                this->xc->regs.intRegFile[i]);
+                this->cpuXC->readIntReg(i));
 
-        this->regFile.setIntReg(renamed_reg, this->xc->regs.intRegFile[i]);
+        this->regFile.setIntReg(renamed_reg, this->cpuXC->readIntReg(i));
     }
 
     // Then loop through the floating point registers.
@@ -220,48 +224,32 @@ AlphaFullCPU<Impl>::copyFromXC()
     {
         renamed_reg = this->renameMap.lookup(i + AlphaISA::FP_Base_DepTag);
         this->regFile.setFloatRegDouble(renamed_reg,
-                                        this->xc->regs.floatRegFile.d[i]);
+                                        this->cpuXC->readFloatRegDouble(i));
         this->regFile.setFloatRegInt(renamed_reg,
-                                     this->xc->regs.floatRegFile.q[i]);
+                                     this->cpuXC->readFloatRegInt(i));
     }
 
     // Then loop through the misc registers.
-    this->regFile.miscRegs.fpcr = this->xc->regs.miscRegs.fpcr;
-    this->regFile.miscRegs.uniq = this->xc->regs.miscRegs.uniq;
-    this->regFile.miscRegs.lock_flag = this->xc->regs.miscRegs.lock_flag;
-    this->regFile.miscRegs.lock_addr = this->xc->regs.miscRegs.lock_addr;
+    this->regFile.setMiscReg(AlphaISA::Fpcr_DepTag,
+                             this->cpuXC->readMiscReg(AlphaISA::Fpcr_DepTag));
+    this->regFile.setMiscReg(AlphaISA::Uniq_DepTag,
+                             this->cpuXC->readMiscReg(AlphaISA::Uniq_DepTag));
+    this->regFile.setMiscReg(AlphaISA::Lock_Flag_DepTag,
+                             this->cpuXC->readMiscReg(AlphaISA::Lock_Flag_DepTag));
+    this->regFile.setMiscReg(AlphaISA::Lock_Addr_DepTag,
+                             this->cpuXC->readMiscReg(AlphaISA::Lock_Addr_DepTag));
 
     // Then finally set the PC and the next PC.
-//    regFile.pc = xc->regs.pc;
-//    regFile.npc = xc->regs.npc;
-
-    this->funcExeInst = this->xc->func_exe_inst;
+//    regFile.pc = cpuXC->regs.pc;
+//    regFile.npc = cpuXC->regs.npc;
+#if !FULL_SYSTEM
+    this->funcExeInst = this->cpuXC->readFuncExeInst();
+#endif
 }
 
 #if FULL_SYSTEM
 
 template <class Impl>
-uint64_t *
-AlphaFullCPU<Impl>::getIpr()
-{
-    return this->regFile.getIpr();
-}
-
-template <class Impl>
-uint64_t
-AlphaFullCPU<Impl>::readIpr(int idx, Fault &fault)
-{
-    return this->regFile.readIpr(idx, fault);
-}
-
-template <class Impl>
-Fault
-AlphaFullCPU<Impl>::setIpr(int idx, uint64_t val)
-{
-    return this->regFile.setIpr(idx, val);
-}
-
-template <class Impl>
 int
 AlphaFullCPU<Impl>::readIntrFlag()
 {
@@ -280,22 +268,20 @@ template <class Impl>
 Fault
 AlphaFullCPU<Impl>::hwrei()
 {
-    uint64_t *ipr = getIpr();
-
     if (!inPalMode())
-        return Unimplemented_Opcode_Fault;
+        return new AlphaISA::UnimplementedOpcodeFault;
 
-    setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]);
+    this->setNextPC(this->regFile.miscRegs.readReg(AlphaISA::IPR_EXC_ADDR));
 
 //    kernelStats.hwrei();
 
-    if ((ipr[AlphaISA::IPR_EXC_ADDR] & 1) == 0)
+    if ((this->regFile.miscRegs.readReg(AlphaISA::IPR_EXC_ADDR) & 1) == 0)
 //        AlphaISA::swap_palshadow(&regs, false);
 
     this->checkInterrupts = true;
 
     // FIXME: XXX check for interrupts? XXX
-    return No_Fault;
+    return NoFault;
 }
 
 template <class Impl>
@@ -328,36 +314,38 @@ template <class Impl>
 void
 AlphaFullCPU<Impl>::trap(Fault fault)
 {
-    // Keep in mind that a trap may be initiated by fetch if there's a TLB
+/*    // Keep in mind that a trap may be initiated by fetch if there's a TLB
     // miss
     uint64_t PC = this->commit.readCommitPC();
 
-    DPRINTF(Fault, "Fault %s\n", FaultName(fault));
-    this->recordEvent(csprintf("Fault %s", FaultName(fault)));
+    DPRINTF(Fault, "Fault %s\n", fault->name());
+    this->recordEvent(csprintf("Fault %s", fault->name()));
 
-//    kernelStats.fault(fault);
+    //kernelStats.fault(fault);
 
-    if (fault == Arithmetic_Fault)
+    if (fault->isA<ArithmeticFault>())
         panic("Arithmetic traps are unimplemented!");
 
-    typename AlphaISA::InternalProcReg *ipr = getIpr();
-
     // exception restart address - Get the commit PC
-    if (fault != Interrupt_Fault || !inPalMode(PC))
-        ipr[AlphaISA::IPR_EXC_ADDR] = PC;
+    if (!fault->isA<InterruptFault>() || !inPalMode(PC))
+        this->regFile.miscRegs.setReg(AlphaISA::IPR_EXC_ADDR, PC);
 
-    if (fault == Pal_Fault || fault == Arithmetic_Fault /* ||
-        fault == Interrupt_Fault && !PC_PAL(regs.pc) */) {
+    if (fault->isA<PalFault>() || fault->isA<ArithmeticFault>())
+    //    || fault == InterruptFault && !PC_PAL(regs.pc)
+        {
         // traps...  skip faulting instruction
-        ipr[AlphaISA::IPR_EXC_ADDR] += 4;
+        AlphaISA::MiscReg ipr_exc_addr =
+            this->regFile.miscRegs.readReg(AlphaISA::IPR_EXC_ADDR);
+        this->regFile.miscRegs.setReg(AlphaISA::IPR_EXC_ADDR,
+                                      ipr_exc_addr + 4);
     }
 
     if (!inPalMode(PC))
         swapPALShadow(true);
 
-    this->regFile.setPC( ipr[AlphaISA::IPR_PAL_BASE] +
-                         AlphaISA::fault_addr[fault] );
-    this->regFile.setNextPC(PC + sizeof(MachInst));
+    this->regFile.setPC(this->regFile.miscRegs.readReg(AlphaISA::IPR_PAL_BASE) +
+                         (dynamic_cast<AlphaFault *>(fault.get()))->vect());
+    this->regFile.setNextPC(PC + sizeof(MachInst));*/
 }
 
 template <class Impl>
diff --git a/cpu/o3/alpha_dyn_inst.hh b/cpu/o3/alpha_dyn_inst.hh
index bb90bf21a..e7f7d3a57 100644
--- a/cpu/o3/alpha_dyn_inst.hh
+++ b/cpu/o3/alpha_dyn_inst.hh
@@ -48,21 +48,18 @@ class AlphaDynInst : public BaseDynInst<Impl>
     /** Typedef for the CPU. */
     typedef typename Impl::FullCPU FullCPU;
 
-    /** Typedef to get the ISA. */
-    typedef typename Impl::ISA ISA;
-
     /** Binary machine instruction type. */
-    typedef typename ISA::MachInst MachInst;
-    /** Memory address type. */
-    typedef typename ISA::Addr	   Addr;
+    typedef TheISA::MachInst MachInst;
     /** Logical register index type. */
-    typedef typename ISA::RegIndex RegIndex;
+    typedef TheISA::RegIndex RegIndex;
     /** Integer register index type. */
-    typedef typename ISA::IntReg   IntReg;
+    typedef TheISA::IntReg   IntReg;
+    /** Misc register index type. */
+    typedef TheISA::MiscReg  MiscReg;
 
     enum {
-        MaxInstSrcRegs = ISA::MaxInstSrcRegs,	//< Max source regs
-        MaxInstDestRegs = ISA::MaxInstDestRegs,	//< Max dest regs
+        MaxInstSrcRegs = TheISA::MaxInstSrcRegs,	//< Max source regs
+        MaxInstDestRegs = TheISA::MaxInstDestRegs,	//< Max dest regs
     };
 
   public:
@@ -71,7 +68,7 @@ class AlphaDynInst : public BaseDynInst<Impl>
                  FullCPU *cpu);
 
     /** BaseDynInst constructor given a static inst pointer. */
-    AlphaDynInst(StaticInstPtr<AlphaISA> &_staticInst);
+    AlphaDynInst(StaticInstPtr &_staticInst);
 
     /** Executes the instruction.*/
     Fault execute()
@@ -80,15 +77,35 @@ class AlphaDynInst : public BaseDynInst<Impl>
     }
 
   public:
-    uint64_t readUniq();
-    void setUniq(uint64_t val);
+    MiscReg readMiscReg(int misc_reg)
+    {
+        // Dummy function for now.
+        // @todo: Fix this once reg file gets fixed.
+        return 0;
+    }
+
+    MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
+    {
+        // Dummy function for now.
+        // @todo: Fix this once reg file gets fixed.
+        return 0;
+    }
 
-    uint64_t readFpcr();
-    void setFpcr(uint64_t val);
+    Fault setMiscReg(int misc_reg, const MiscReg &val)
+    {
+        // Dummy function for now.
+        // @todo: Fix this once reg file gets fixed.
+        return NoFault;
+    }
+
+    Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
+    {
+        // Dummy function for now.
+        // @todo: Fix this once reg file gets fixed.
+        return NoFault;
+    }
 
 #if FULL_SYSTEM
-    uint64_t readIpr(int idx, Fault &fault);
-    Fault setIpr(int idx, uint64_t val);
     Fault hwrei();
     int readIntrFlag();
     void setIntrFlag(int val);
@@ -130,22 +147,22 @@ class AlphaDynInst : public BaseDynInst<Impl>
     // storage (which is pretty hard to imagine they would have reason
     // to do).
 
-    uint64_t readIntReg(const StaticInst<ISA> *si, int idx)
+    uint64_t readIntReg(const StaticInst *si, int idx)
     {
         return this->cpu->readIntReg(_srcRegIdx[idx]);
     }
 
-    float readFloatRegSingle(const StaticInst<ISA> *si, int idx)
+    float readFloatRegSingle(const StaticInst *si, int idx)
     {
         return this->cpu->readFloatRegSingle(_srcRegIdx[idx]);
     }
 
-    double readFloatRegDouble(const StaticInst<ISA> *si, int idx)
+    double readFloatRegDouble(const StaticInst *si, int idx)
     {
         return this->cpu->readFloatRegDouble(_srcRegIdx[idx]);
     }
 
-    uint64_t readFloatRegInt(const StaticInst<ISA> *si, int idx)
+    uint64_t readFloatRegInt(const StaticInst *si, int idx)
     {
         return this->cpu->readFloatRegInt(_srcRegIdx[idx]);
     }
@@ -153,25 +170,25 @@ class AlphaDynInst : public BaseDynInst<Impl>
     /** @todo: Make results into arrays so they can handle multiple dest
      *  registers.
      */
-    void setIntReg(const StaticInst<ISA> *si, int idx, uint64_t val)
+    void setIntReg(const StaticInst *si, int idx, uint64_t val)
     {
         this->cpu->setIntReg(_destRegIdx[idx], val);
         this->instResult.integer = val;
     }
 
-    void setFloatRegSingle(const StaticInst<ISA> *si, int idx, float val)
+    void setFloatRegSingle(const StaticInst *si, int idx, float val)
     {
         this->cpu->setFloatRegSingle(_destRegIdx[idx], val);
         this->instResult.fp = val;
     }
 
-    void setFloatRegDouble(const StaticInst<ISA> *si, int idx, double val)
+    void setFloatRegDouble(const StaticInst *si, int idx, double val)
     {
         this->cpu->setFloatRegDouble(_destRegIdx[idx], val);
         this->instResult.dbl = val;
     }
 
-    void setFloatRegInt(const StaticInst<ISA> *si, int idx, uint64_t val)
+    void setFloatRegInt(const StaticInst *si, int idx, uint64_t val)
     {
         this->cpu->setFloatRegInt(_destRegIdx[idx], val);
         this->instResult.integer = val;
diff --git a/cpu/o3/alpha_dyn_inst_impl.hh b/cpu/o3/alpha_dyn_inst_impl.hh
index d1ebb812d..96b7d3430 100644
--- a/cpu/o3/alpha_dyn_inst_impl.hh
+++ b/cpu/o3/alpha_dyn_inst_impl.hh
@@ -50,7 +50,7 @@ AlphaDynInst<Impl>::AlphaDynInst(MachInst inst, Addr PC, Addr Pred_PC,
 }
 
 template <class Impl>
-AlphaDynInst<Impl>::AlphaDynInst(StaticInstPtr<AlphaISA> &_staticInst)
+AlphaDynInst<Impl>::AlphaDynInst(StaticInstPtr &_staticInst)
     : BaseDynInst<Impl>(_staticInst)
 {
     // Make sure to have the renamed register entries set to the same
@@ -67,50 +67,8 @@ AlphaDynInst<Impl>::AlphaDynInst(StaticInstPtr<AlphaISA> &_staticInst)
     }
 }
 
-template <class Impl>
-uint64_t
-AlphaDynInst<Impl>::readUniq()
-{
-    return this->cpu->readUniq();
-}
-
-template <class Impl>
-void
-AlphaDynInst<Impl>::setUniq(uint64_t val)
-{
-    this->cpu->setUniq(val);
-}
-
-template <class Impl>
-uint64_t
-AlphaDynInst<Impl>::readFpcr()
-{
-    return this->cpu->readFpcr();
-}
-
-template <class Impl>
-void
-AlphaDynInst<Impl>::setFpcr(uint64_t val)
-{
-    this->cpu->setFpcr(val);
-}
-
 #if FULL_SYSTEM
 template <class Impl>
-uint64_t
-AlphaDynInst<Impl>::readIpr(int idx, Fault &fault)
-{
-    return this->cpu->readIpr(idx, fault);
-}
-
-template <class Impl>
-Fault
-AlphaDynInst<Impl>::setIpr(int idx, uint64_t val)
-{
-    return this->cpu->setIpr(idx, val);
-}
-
-template <class Impl>
 Fault
 AlphaDynInst<Impl>::hwrei()
 {
diff --git a/cpu/o3/alpha_impl.hh b/cpu/o3/alpha_impl.hh
index 6c1156041..5e39fcb37 100644
--- a/cpu/o3/alpha_impl.hh
+++ b/cpu/o3/alpha_impl.hh
@@ -51,11 +51,8 @@ class AlphaFullCPU;
  */
 struct AlphaSimpleImpl
 {
-    /** The ISA to be used. */
-    typedef AlphaISA ISA;
-
     /** The type of MachInst. */
-    typedef ISA::MachInst MachInst;
+    typedef TheISA::MachInst MachInst;
 
     /** The CPU policy to be used (ie fetch, decode, etc.). */
     typedef SimpleCPUPolicy<AlphaSimpleImpl> CPUPol;
diff --git a/cpu/o3/bpred_unit.hh b/cpu/o3/bpred_unit.hh
index 0a77b83dc..2725684f7 100644
--- a/cpu/o3/bpred_unit.hh
+++ b/cpu/o3/bpred_unit.hh
@@ -30,7 +30,7 @@
 #define __BPRED_UNIT_HH__
 
 // For Addr type.
-#include "arch/alpha/isa_traits.hh"
+#include "arch/isa_traits.hh"
 #include "base/statistics.hh"
 #include "cpu/inst_seq.hh"
 
diff --git a/cpu/o3/bpred_unit_impl.hh b/cpu/o3/bpred_unit_impl.hh
index 9cb2e0490..8d16a0cdf 100644
--- a/cpu/o3/bpred_unit_impl.hh
+++ b/cpu/o3/bpred_unit_impl.hh
@@ -98,6 +98,8 @@ TwobitBPredUnit<Impl>::predict(DynInstPtr &inst, Addr &PC)
     // Save off record of branch stuff so the RAS can be fixed
     // up once it's done.
 
+    using TheISA::MachInst;
+
     bool pred_taken = false;
     Addr target;
 
diff --git a/cpu/o3/btb.cc b/cpu/o3/btb.cc
index 7671e61e2..2d39c3856 100644
--- a/cpu/o3/btb.cc
+++ b/cpu/o3/btb.cc
@@ -30,6 +30,8 @@
 #include "base/trace.hh"
 #include "cpu/o3/btb.hh"
 
+using namespace TheISA;
+
 DefaultBTB::DefaultBTB(unsigned _numEntries,
                        unsigned _tagBits,
                        unsigned _instShiftAmt)
diff --git a/cpu/o3/btb.hh b/cpu/o3/btb.hh
index a4ddfecb4..77bdc32ea 100644
--- a/cpu/o3/btb.hh
+++ b/cpu/o3/btb.hh
@@ -30,7 +30,7 @@
 #define __CPU_O3_CPU_BTB_HH__
 
 // For Addr type.
-#include "arch/alpha/isa_traits.hh"
+#include "arch/isa_traits.hh"
 
 class DefaultBTB
 {
diff --git a/cpu/o3/comm.hh b/cpu/o3/comm.hh
index e4de1d304..c74c77ddf 100644
--- a/cpu/o3/comm.hh
+++ b/cpu/o3/comm.hh
@@ -31,7 +31,7 @@
 
 #include <vector>
 
-#include "arch/alpha/isa_traits.hh"
+#include "arch/isa_traits.hh"
 #include "cpu/inst_seq.hh"
 #include "sim/host.hh"
 
diff --git a/cpu/o3/commit.hh b/cpu/o3/commit.hh
index 6ddc8d6b9..580c1a316 100644
--- a/cpu/o3/commit.hh
+++ b/cpu/o3/commit.hh
@@ -52,7 +52,6 @@ class SimpleCommit
 {
   public:
     // Typedefs from the Impl.
-    typedef typename Impl::ISA ISA;
     typedef typename Impl::FullCPU FullCPU;
     typedef typename Impl::DynInstPtr DynInstPtr;
     typedef typename Impl::Params Params;
diff --git a/cpu/o3/commit_impl.hh b/cpu/o3/commit_impl.hh
index dc0986772..e289bc0c0 100644
--- a/cpu/o3/commit_impl.hh
+++ b/cpu/o3/commit_impl.hh
@@ -395,7 +395,7 @@ SimpleCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
     // Check if the instruction caused a fault.  If so, trap.
     Fault inst_fault = head_inst->getFault();
 
-    if (inst_fault != No_Fault && inst_fault != Fake_Mem_Fault) {
+    if (inst_fault != NoFault) {
         if (!head_inst->isNop()) {
 #if FULL_SYSTEM
             cpu->trap(inst_fault);
diff --git a/cpu/o3/cpu.cc b/cpu/o3/cpu.cc
index adc7b6bbc..62d68bb33 100644
--- a/cpu/o3/cpu.cc
+++ b/cpu/o3/cpu.cc
@@ -35,10 +35,11 @@
 #endif
 #include "sim/root.hh"
 
+#include "cpu/cpu_exec_context.hh"
+#include "cpu/exec_context.hh"
 #include "cpu/o3/alpha_dyn_inst.hh"
 #include "cpu/o3/alpha_impl.hh"
 #include "cpu/o3/cpu.hh"
-#include "cpu/exec_context.hh"
 
 using namespace std;
 
@@ -84,14 +85,14 @@ FullO3CPU<Impl>::FullO3CPU(Params &params)
 
       regFile(params.numPhysIntRegs, params.numPhysFloatRegs),
 
-      freeList(Impl::ISA::NumIntRegs, params.numPhysIntRegs,
-               Impl::ISA::NumFloatRegs, params.numPhysFloatRegs),
+      freeList(TheISA::NumIntRegs, params.numPhysIntRegs,
+               TheISA::NumFloatRegs, params.numPhysFloatRegs),
 
-      renameMap(Impl::ISA::NumIntRegs, params.numPhysIntRegs,
-                Impl::ISA::NumFloatRegs, params.numPhysFloatRegs,
-                Impl::ISA::NumMiscRegs,
-                Impl::ISA::ZeroReg,
-                Impl::ISA::ZeroReg + Impl::ISA::NumIntRegs),
+      renameMap(TheISA::NumIntRegs, params.numPhysIntRegs,
+                TheISA::NumFloatRegs, params.numPhysFloatRegs,
+                TheISA::NumMiscRegs,
+                TheISA::ZeroReg,
+                TheISA::ZeroReg + TheISA::NumIntRegs),
 
       rob(params.numROBEntries, params.squashWidth),
 
@@ -103,7 +104,7 @@ FullO3CPU<Impl>::FullO3CPU(Params &params)
       renameQueue(5, 5),
       iewQueue(5, 5),
 
-      xc(NULL),
+      cpuXC(NULL),
 
       globalSeqNum(1),
 
@@ -134,32 +135,26 @@ FullO3CPU<Impl>::FullO3CPU(Params &params)
     for (int i = 0; i < this->number_of_threads; ++i) {
 #if FULL_SYSTEM
         assert(i == 0);
-        system->execContexts[i] =
-            new ExecContext(this, i, system, itb, dtb, mem);
+        thread[i] = new CPUExecContext(this, 0, system, itb, dtb, mem);
+        system->execContexts[i] = thread[i]->getProxy();
 
-        // initialize CPU, including PC
-        TheISA::initCPU(&system->execContexts[i]->regs);
         execContexts.push_back(system->execContexts[i]);
 #else
         if (i < params.workload.size()) {
             DPRINTF(FullCPU, "FullCPU: Workload[%i]'s starting PC is %#x, "
                     "process is %#x",
                     i, params.workload[i]->prog_entry, thread[i]);
-            thread[i] = new ExecContext(this, i, params.workload[i], i);
+            thread[i] = new CPUExecContext(this, i, params.workload[i], i);
         }
         assert(params.workload[i]->getMemory() != NULL);
         assert(mem != NULL);
-        execContexts.push_back(thread[i]);
+        execContexts.push_back(thread[i]->getProxy());
 #endif // !FULL_SYSTEM
     }
 
     // Note that this is a hack so that my code which still uses xc-> will
     // still work.  I should remove this eventually
-#if FULL_SYSTEM
-    xc = system->execContexts[0];
-#else
-    xc = thread[0];
-#endif
+    cpuXC = thread[0];
 
     // The stages also need their CPU pointer setup.  However this must be
     // done at the upper level CPU because they have pointers to the upper
@@ -250,31 +245,32 @@ FullO3CPU<Impl>::init()
         // that it can start properly.
 #if FULL_SYSTEM
         ExecContext *src_xc = system->execContexts[0];
+        TheISA::initCPU(src_xc, src_xc->readCpuId());
 #else
-        ExecContext *src_xc = thread[0];
+        ExecContext *src_xc = thread[0]->getProxy();
 #endif
         // First loop through the integer registers.
-        for (int i = 0; i < Impl::ISA::NumIntRegs; ++i)
+        for (int i = 0; i < TheISA::NumIntRegs; ++i)
         {
-            regFile.intRegFile[i] = src_xc->regs.intRegFile[i];
+            regFile.intRegFile[i] = src_xc->readIntReg(i);
         }
 
         // Then loop through the floating point registers.
-        for (int i = 0; i < Impl::ISA::NumFloatRegs; ++i)
+        for (int i = 0; i < TheISA::NumFloatRegs; ++i)
         {
-            regFile.floatRegFile[i].d = src_xc->regs.floatRegFile.d[i];
-            regFile.floatRegFile[i].q = src_xc->regs.floatRegFile.q[i];
+            regFile.floatRegFile[i].d = src_xc->readFloatRegDouble(i);
+            regFile.floatRegFile[i].q = src_xc->readFloatRegInt(i);
         }
-
+/*
         // Then loop through the misc registers.
         regFile.miscRegs.fpcr = src_xc->regs.miscRegs.fpcr;
         regFile.miscRegs.uniq = src_xc->regs.miscRegs.uniq;
         regFile.miscRegs.lock_flag = src_xc->regs.miscRegs.lock_flag;
         regFile.miscRegs.lock_addr = src_xc->regs.miscRegs.lock_addr;
-
+*/
         // Then finally set the PC and the next PC.
-        regFile.pc = src_xc->regs.pc;
-        regFile.npc = src_xc->regs.npc;
+        regFile.pc = src_xc->readPC();
+        regFile.npc = src_xc->readNextPC();
     }
 }
 
diff --git a/cpu/o3/cpu.hh b/cpu/o3/cpu.hh
index 75dca5056..6577e46e4 100644
--- a/cpu/o3/cpu.hh
+++ b/cpu/o3/cpu.hh
@@ -44,16 +44,12 @@
 #include "base/timebuf.hh"
 #include "config/full_system.hh"
 #include "cpu/base.hh"
+#include "cpu/cpu_exec_context.hh"
 #include "cpu/o3/comm.hh"
 #include "cpu/o3/cpu_policy.hh"
-#include "cpu/exec_context.hh"
 #include "sim/process.hh"
 
-#if FULL_SYSTEM
-#include "arch/alpha/ev5.hh"
-using namespace EV5;
-#endif
-
+class ExecContext;
 class FunctionalMemory;
 class Process;
 
@@ -78,7 +74,6 @@ class FullO3CPU : public BaseFullCPU
 {
   public:
     //Put typedefs from the Impl here.
-    typedef typename Impl::ISA ISA;
     typedef typename Impl::CPUPol CPUPolicy;
     typedef typename Impl::Params Params;
     typedef typename Impl::DynInstPtr DynInstPtr;
@@ -153,11 +148,11 @@ class FullO3CPU : public BaseFullCPU
 
     /** Get instruction asid. */
     int getInstAsid()
-    { return ITB_ASN_ASN(regFile.getIpr()[ISA::IPR_ITB_ASN]); }
+    { return regFile.miscRegs.getInstAsid(); }
 
     /** Get data asid. */
     int getDataAsid()
-    { return DTB_ASN_ASN(regFile.getIpr()[ISA::IPR_DTB_ASN]); }
+    { return regFile.miscRegs.getDataAsid(); }
 #else
     bool validInstAddr(Addr addr)
     { return thread[0]->validInstAddr(addr); }
@@ -165,8 +160,8 @@ class FullO3CPU : public BaseFullCPU
     bool validDataAddr(Addr addr)
     { return thread[0]->validDataAddr(addr); }
 
-    int getInstAsid() { return thread[0]->asid; }
-    int getDataAsid() { return thread[0]->asid; }
+    int getInstAsid() { return thread[0]->getInstAsid(); }
+    int getDataAsid() { return thread[0]->getDataAsid(); }
 
 #endif
 
@@ -321,16 +316,17 @@ class FullO3CPU : public BaseFullCPU
 
   public:
     /** The temporary exec context to support older accessors. */
-    ExecContext *xc;
+    CPUExecContext *cpuXC;
 
     /** Temporary function to get pointer to exec context. */
     ExecContext *xcBase()
     {
-#if FULL_SYSTEM
-        return system->execContexts[0];
-#else
+        return thread[0]->getProxy();
+    }
+
+    CPUExecContext *cpuXCBase()
+    {
         return thread[0];
-#endif
     }
 
     InstSeqNum globalSeqNum;
@@ -345,9 +341,8 @@ class FullO3CPU : public BaseFullCPU
     AlphaDTB *dtb;
 
 //    SWContext *swCtx;
-#else
-    std::vector<ExecContext *> thread;
 #endif
+    std::vector<CPUExecContext *> thread;
 
     FunctionalMemory *mem;
 
diff --git a/cpu/o3/decode.hh b/cpu/o3/decode.hh
index 42313d83a..5b9a0f822 100644
--- a/cpu/o3/decode.hh
+++ b/cpu/o3/decode.hh
@@ -39,7 +39,6 @@ class SimpleDecode
 {
   private:
     // Typedefs from the Impl.
-    typedef typename Impl::ISA ISA;
     typedef typename Impl::FullCPU FullCPU;
     typedef typename Impl::DynInstPtr DynInstPtr;
     typedef typename Impl::Params Params;
@@ -50,9 +49,6 @@ class SimpleDecode
     typedef typename CPUPol::DecodeStruct DecodeStruct;
     typedef typename CPUPol::TimeStruct TimeStruct;
 
-    // Typedefs from the ISA.
-    typedef typename ISA::Addr Addr;
-
   public:
     // The only time decode will become blocked is if dispatch becomes
     // blocked, which means IQ or ROB is probably full.
diff --git a/cpu/o3/fetch.hh b/cpu/o3/fetch.hh
index 24e445f0b..cc64800d9 100644
--- a/cpu/o3/fetch.hh
+++ b/cpu/o3/fetch.hh
@@ -49,7 +49,6 @@ class SimpleFetch
 {
   public:
     /** Typedefs from Impl. */
-    typedef typename Impl::ISA ISA;
     typedef typename Impl::CPUPol CPUPol;
     typedef typename Impl::DynInst DynInst;
     typedef typename Impl::DynInstPtr DynInstPtr;
@@ -61,7 +60,7 @@ class SimpleFetch
     typedef typename CPUPol::TimeStruct TimeStruct;
 
     /** Typedefs from ISA. */
-    typedef typename ISA::MachInst MachInst;
+    typedef TheISA::MachInst MachInst;
 
   public:
     enum Status {
@@ -141,7 +140,7 @@ class SimpleFetch
     // We fold in the PISA 64- to 32-bit conversion here as well.
     Addr icacheBlockAlignPC(Addr addr)
     {
-        addr = ISA::realPCToFetchPC(addr);
+        addr = TheISA::realPCToFetchPC(addr);
         return (addr & ~(cacheBlkMask));
     }
 
diff --git a/cpu/o3/fetch_impl.hh b/cpu/o3/fetch_impl.hh
index c943fd36a..8029fc732 100644
--- a/cpu/o3/fetch_impl.hh
+++ b/cpu/o3/fetch_impl.hh
@@ -29,8 +29,8 @@
 // Remove this later; used only for debugging.
 #define OPCODE(X)                       (X >> 26) & 0x3f
 
-
-#include "arch/alpha/byte_swap.hh"
+#include "arch/isa_traits.hh"
+#include "sim/byteswap.hh"
 #include "cpu/exetrace.hh"
 #include "mem/base_mem.hh"
 #include "mem/mem_interface.hh"
@@ -236,7 +236,7 @@ SimpleFetch<Impl>::fetchCacheLine(Addr fetch_PC)
     unsigned flags = 0;
 #endif // FULL_SYSTEM
 
-    Fault fault = No_Fault;
+    Fault fault = NoFault;
 
     // Align the fetch PC so it's at the start of a cache block.
     fetch_PC = icacheBlockAlignPC(fetch_PC);
@@ -258,7 +258,7 @@ SimpleFetch<Impl>::fetchCacheLine(Addr fetch_PC)
 
     // If translation was successful, attempt to read the first
     // instruction.
-    if (fault == No_Fault) {
+    if (fault == NoFault) {
         DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
         fault = cpu->mem->read(memReq, cacheData);
         // This read may change when the mem interface changes.
@@ -268,7 +268,7 @@ SimpleFetch<Impl>::fetchCacheLine(Addr fetch_PC)
 
     // Now do the timing access to see whether or not the instruction
     // exists within the cache.
-    if (icacheInterface && fault == No_Fault) {
+    if (icacheInterface && fault == NoFault) {
         DPRINTF(Fetch, "Fetch: Doing timing memory access.\n");
         memReq->completionEvent = NULL;
 
@@ -468,7 +468,7 @@ SimpleFetch<Impl>::fetch()
     Addr fetch_PC = cpu->readPC();
 
     // Fault code for memory access.
-    Fault fault = No_Fault;
+    Fault fault = NoFault;
 
     // If returning from the delay of a cache miss, then update the status
     // to running, otherwise do the cache access.  Possibly move this up
@@ -506,7 +506,7 @@ SimpleFetch<Impl>::fetch()
     unsigned offset = fetch_PC & cacheBlkMask;
     unsigned fetched;
 
-    if (fault == No_Fault) {
+    if (fault == NoFault) {
         // If the read of the first instruction was successful, then grab the
         // instructions from the rest of the cache line and put them into the
         // queue heading to decode.
@@ -582,7 +582,7 @@ SimpleFetch<Impl>::fetch()
     // Or might want to leave setting the PC to the main CPU, with fetch
     // only changing the nextPC (will require correct determination of
     // next PC).
-    if (fault == No_Fault) {
+    if (fault == NoFault) {
         DPRINTF(Fetch, "Fetch: Setting PC to %08p.\n", next_PC);
         cpu->setPC(next_PC);
         cpu->setNextPC(next_PC + instSize);
diff --git a/cpu/o3/free_list.hh b/cpu/o3/free_list.hh
index 733d142fc..0b85dba1e 100644
--- a/cpu/o3/free_list.hh
+++ b/cpu/o3/free_list.hh
@@ -32,7 +32,7 @@
 #include <iostream>
 #include <queue>
 
-#include "arch/alpha/isa_traits.hh"
+#include "arch/isa_traits.hh"
 #include "base/trace.hh"
 #include "base/traceflags.hh"
 #include "cpu/o3/comm.hh"
diff --git a/cpu/o3/iew.hh b/cpu/o3/iew.hh
index af23c6f45..1e370d4e6 100644
--- a/cpu/o3/iew.hh
+++ b/cpu/o3/iew.hh
@@ -45,7 +45,6 @@ class SimpleIEW
 {
   private:
     //Typedefs from Impl
-    typedef typename Impl::ISA ISA;
     typedef typename Impl::CPUPol CPUPol;
     typedef typename Impl::DynInstPtr DynInstPtr;
     typedef typename Impl::FullCPU FullCPU;
diff --git a/cpu/o3/iew_impl.hh b/cpu/o3/iew_impl.hh
index b8a2b4dc9..85217dd10 100644
--- a/cpu/o3/iew_impl.hh
+++ b/cpu/o3/iew_impl.hh
@@ -256,7 +256,7 @@ SimpleIEW<Impl>::squashDueToBranch(DynInstPtr &inst)
     toCommit->branchMispredict = true;
     // Prediction was incorrect, so send back inverse.
     toCommit->branchTaken = inst->readNextPC() !=
-        (inst->readPC() + sizeof(MachInst));
+        (inst->readPC() + sizeof(TheISA::MachInst));
 }
 
 template<class Impl>
diff --git a/cpu/o3/inst_queue_impl.hh b/cpu/o3/inst_queue_impl.hh
index 2221ba456..048dc7c00 100644
--- a/cpu/o3/inst_queue_impl.hh
+++ b/cpu/o3/inst_queue_impl.hh
@@ -34,6 +34,7 @@
 // but probably is more flexible to actually add in a delay parameter than
 // just running it backwards.
 
+#include <limits>
 #include <vector>
 
 #include "sim/root.hh"
@@ -42,7 +43,7 @@
 
 // Either compile error or max int due to sign extension.
 // Hack to avoid compile warnings.
-const InstSeqNum MaxInstSeqNum = 0 - 1;
+const InstSeqNum MaxInstSeqNum = std::numeric_limits<InstSeqNum>::max();
 
 template <class Impl>
 InstructionQueue<Impl>::InstructionQueue(Params &params)
diff --git a/cpu/o3/ras.hh b/cpu/o3/ras.hh
index bbc4162a6..46d98181e 100644
--- a/cpu/o3/ras.hh
+++ b/cpu/o3/ras.hh
@@ -30,7 +30,7 @@
 #define __CPU_O3_CPU_RAS_HH__
 
 // For Addr type.
-#include "arch/alpha/isa_traits.hh"
+#include "arch/isa_traits.hh"
 
 class ReturnAddrStack
 {
diff --git a/cpu/o3/regfile.hh b/cpu/o3/regfile.hh
index 4d47b8f9c..1e6e10f29 100644
--- a/cpu/o3/regfile.hh
+++ b/cpu/o3/regfile.hh
@@ -31,16 +31,15 @@
 
 // @todo: Destructor
 
-#include "arch/alpha/isa_traits.hh"
+#include "arch/isa_traits.hh"
+#include "arch/faults.hh"
 #include "base/trace.hh"
 #include "config/full_system.hh"
 #include "cpu/o3/comm.hh"
 
 #if FULL_SYSTEM
-#include "arch/alpha/ev5.hh"
 #include "kern/kernel_stats.hh"
 
-using namespace EV5;
 #endif
 
 // This really only depends on the ISA, and not the Impl.  It might be nicer
@@ -51,6 +50,12 @@ using namespace EV5;
 template <class Impl>
 class PhysRegFile
 {
+  protected:
+    typedef TheISA::IntReg IntReg;
+    typedef TheISA::FloatReg FloatReg;
+    typedef TheISA::MiscRegFile MiscRegFile;
+    typedef TheISA::MiscReg MiscReg;
+
     //Note that most of the definitions of the IntReg, FloatReg, etc. exist
     //within the Impl/ISA class and not within this PhysRegFile class.
 
@@ -61,7 +66,6 @@ class PhysRegFile
     //Will make these registers public for now, but they probably should
     //be private eventually with some accessor functions.
   public:
-    typedef typename Impl::ISA ISA;
     typedef typename Impl::FullCPU FullCPU;
 
     PhysRegFile(unsigned _numPhysicalIntRegs,
@@ -190,30 +194,21 @@ class PhysRegFile
 
     //Consider leaving this stuff and below in some implementation specific
     //file as opposed to the general register file.  Or have a derived class.
-    uint64_t readUniq()
-    {
-        return miscRegs.uniq;
-    }
-
-    void setUniq(uint64_t val)
-    {
-        miscRegs.uniq = val;
-    }
-
-    uint64_t readFpcr()
+    MiscReg readMiscReg(int misc_reg)
     {
-        return miscRegs.fpcr;
+        // Dummy function for now.
+        // @todo: Fix this once proxy XC is used.
+        return 0;
     }
 
-    void setFpcr(uint64_t val)
+    Fault setMiscReg(int misc_reg, const MiscReg &val)
     {
-        miscRegs.fpcr = val;
+        // Dummy function for now.
+        // @todo: Fix this once proxy XC is used.
+        return NoFault;
     }
 
 #if FULL_SYSTEM
-    uint64_t readIpr(int idx, Fault &fault);
-    Fault setIpr(int idx, uint64_t val);
-    InternalProcReg *getIpr() { return ipr; }
     int readIntrFlag() { return intrflag; }
     void setIntrFlag(int val) { intrflag = val; }
 #endif
@@ -239,8 +234,7 @@ class PhysRegFile
 #if FULL_SYSTEM
   private:
     // This is ISA specifc stuff; remove it eventually once ISAImpl is used
-    IntReg palregs[NumIntRegs];	// PAL shadow registers
-    InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs
+//    IntReg palregs[NumIntRegs];	// PAL shadow registers
     int intrflag;			// interrupt flag
     bool pal_shadow;		// using pal_shadow registers
 #endif
@@ -268,368 +262,4 @@ PhysRegFile<Impl>::PhysRegFile(unsigned _numPhysicalIntRegs,
     memset(floatRegFile, 0, sizeof(*floatRegFile));
 }
 
-#if FULL_SYSTEM
-
-//Problem:  This code doesn't make sense at the RegFile level because it
-//needs things such as the itb and dtb.  Either put it at the CPU level or
-//the DynInst level.
-template <class Impl>
-uint64_t
-PhysRegFile<Impl>::readIpr(int idx, Fault &fault)
-{
-    uint64_t retval = 0;    // return value, default 0
-
-    switch (idx) {
-      case ISA::IPR_PALtemp0:
-      case ISA::IPR_PALtemp1:
-      case ISA::IPR_PALtemp2:
-      case ISA::IPR_PALtemp3:
-      case ISA::IPR_PALtemp4:
-      case ISA::IPR_PALtemp5:
-      case ISA::IPR_PALtemp6:
-      case ISA::IPR_PALtemp7:
-      case ISA::IPR_PALtemp8:
-      case ISA::IPR_PALtemp9:
-      case ISA::IPR_PALtemp10:
-      case ISA::IPR_PALtemp11:
-      case ISA::IPR_PALtemp12:
-      case ISA::IPR_PALtemp13:
-      case ISA::IPR_PALtemp14:
-      case ISA::IPR_PALtemp15:
-      case ISA::IPR_PALtemp16:
-      case ISA::IPR_PALtemp17:
-      case ISA::IPR_PALtemp18:
-      case ISA::IPR_PALtemp19:
-      case ISA::IPR_PALtemp20:
-      case ISA::IPR_PALtemp21:
-      case ISA::IPR_PALtemp22:
-      case ISA::IPR_PALtemp23:
-      case ISA::IPR_PAL_BASE:
-
-      case ISA::IPR_IVPTBR:
-      case ISA::IPR_DC_MODE:
-      case ISA::IPR_MAF_MODE:
-      case ISA::IPR_ISR:
-      case ISA::IPR_EXC_ADDR:
-      case ISA::IPR_IC_PERR_STAT:
-      case ISA::IPR_DC_PERR_STAT:
-      case ISA::IPR_MCSR:
-      case ISA::IPR_ASTRR:
-      case ISA::IPR_ASTER:
-      case ISA::IPR_SIRR:
-      case ISA::IPR_ICSR:
-      case ISA::IPR_ICM:
-      case ISA::IPR_DTB_CM:
-      case ISA::IPR_IPLR:
-      case ISA::IPR_INTID:
-      case ISA::IPR_PMCTR:
-        // no side-effect
-        retval = ipr[idx];
-        break;
-
-      case ISA::IPR_CC:
-        retval |= ipr[idx] & ULL(0xffffffff00000000);
-        retval |= curTick  & ULL(0x00000000ffffffff);
-        break;
-
-      case ISA::IPR_VA:
-        retval = ipr[idx];
-        break;
-
-      case ISA::IPR_VA_FORM:
-      case ISA::IPR_MM_STAT:
-      case ISA::IPR_IFAULT_VA_FORM:
-      case ISA::IPR_EXC_MASK:
-      case ISA::IPR_EXC_SUM:
-        retval = ipr[idx];
-        break;
-
-      case ISA::IPR_DTB_PTE:
-        {
-            typename ISA::PTE &pte = cpu->dtb->index(1);
-
-            retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
-            retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
-            retval |= ((u_int64_t)pte.xwe & ULL(0xf)) << 12;
-            retval |= ((u_int64_t)pte.fonr & ULL(0x1)) << 1;
-            retval |= ((u_int64_t)pte.fonw & ULL(0x1))<< 2;
-            retval |= ((u_int64_t)pte.asma & ULL(0x1)) << 4;
-            retval |= ((u_int64_t)pte.asn & ULL(0x7f)) << 57;
-        }
-        break;
-
-        // write only registers
-      case ISA::IPR_HWINT_CLR:
-      case ISA::IPR_SL_XMIT:
-      case ISA::IPR_DC_FLUSH:
-      case ISA::IPR_IC_FLUSH:
-      case ISA::IPR_ALT_MODE:
-      case ISA::IPR_DTB_IA:
-      case ISA::IPR_DTB_IAP:
-      case ISA::IPR_ITB_IA:
-      case ISA::IPR_ITB_IAP:
-        fault = Unimplemented_Opcode_Fault;
-        break;
-
-      default:
-        // invalid IPR
-        fault = Unimplemented_Opcode_Fault;
-        break;
-    }
-
-    return retval;
-}
-
-extern int break_ipl;
-
-template <class Impl>
-Fault
-PhysRegFile<Impl>::setIpr(int idx, uint64_t val)
-{
-    uint64_t old;
-
-    switch (idx) {
-      case ISA::IPR_PALtemp0:
-      case ISA::IPR_PALtemp1:
-      case ISA::IPR_PALtemp2:
-      case ISA::IPR_PALtemp3:
-      case ISA::IPR_PALtemp4:
-      case ISA::IPR_PALtemp5:
-      case ISA::IPR_PALtemp6:
-      case ISA::IPR_PALtemp7:
-      case ISA::IPR_PALtemp8:
-      case ISA::IPR_PALtemp9:
-      case ISA::IPR_PALtemp10:
-      case ISA::IPR_PALtemp11:
-      case ISA::IPR_PALtemp12:
-      case ISA::IPR_PALtemp13:
-      case ISA::IPR_PALtemp14:
-      case ISA::IPR_PALtemp15:
-      case ISA::IPR_PALtemp16:
-      case ISA::IPR_PALtemp17:
-      case ISA::IPR_PALtemp18:
-      case ISA::IPR_PALtemp19:
-      case ISA::IPR_PALtemp20:
-      case ISA::IPR_PALtemp21:
-      case ISA::IPR_PALtemp22:
-      case ISA::IPR_PAL_BASE:
-      case ISA::IPR_IC_PERR_STAT:
-      case ISA::IPR_DC_PERR_STAT:
-      case ISA::IPR_PMCTR:
-        // write entire quad w/ no side-effect
-        ipr[idx] = val;
-        break;
-
-      case ISA::IPR_CC_CTL:
-        // This IPR resets the cycle counter.  We assume this only
-        // happens once... let's verify that.
-        assert(ipr[idx] == 0);
-        ipr[idx] = 1;
-        break;
-
-      case ISA::IPR_CC:
-        // This IPR only writes the upper 64 bits.  It's ok to write
-        // all 64 here since we mask out the lower 32 in rpcc (see
-        // isa_desc).
-        ipr[idx] = val;
-        break;
-
-      case ISA::IPR_PALtemp23:
-        // write entire quad w/ no side-effect
-        old = ipr[idx];
-        ipr[idx] = val;
-        break;
-
-      case ISA::IPR_DTB_PTE:
-        // write entire quad w/ no side-effect, tag is forthcoming
-        ipr[idx] = val;
-        break;
-
-      case ISA::IPR_EXC_ADDR:
-        // second least significant bit in PC is always zero
-        ipr[idx] = val & ~2;
-        break;
-
-      case ISA::IPR_ASTRR:
-      case ISA::IPR_ASTER:
-        // only write least significant four bits - privilege mask
-        ipr[idx] = val & 0xf;
-        break;
-
-      case ISA::IPR_IPLR:
-        // only write least significant five bits - interrupt level
-        ipr[idx] = val & 0x1f;
-        break;
-
-      case ISA::IPR_DTB_CM:
-
-      case ISA::IPR_ICM:
-        // only write two mode bits - processor mode
-        ipr[idx] = val & 0x18;
-        break;
-
-      case ISA::IPR_ALT_MODE:
-        // only write two mode bits - processor mode
-        ipr[idx] = val & 0x18;
-        break;
-
-      case ISA::IPR_MCSR:
-        // more here after optimization...
-        ipr[idx] = val;
-        break;
-
-      case ISA::IPR_SIRR:
-        // only write software interrupt mask
-        ipr[idx] = val & 0x7fff0;
-        break;
-
-      case ISA::IPR_ICSR:
-        ipr[idx] = val & ULL(0xffffff0300);
-        break;
-
-      case ISA::IPR_IVPTBR:
-      case ISA::IPR_MVPTBR:
-        ipr[idx] = val & ULL(0xffffffffc0000000);
-        break;
-
-      case ISA::IPR_DC_TEST_CTL:
-        ipr[idx] = val & 0x1ffb;
-        break;
-
-      case ISA::IPR_DC_MODE:
-      case ISA::IPR_MAF_MODE:
-        ipr[idx] = val & 0x3f;
-        break;
-
-      case ISA::IPR_ITB_ASN:
-        ipr[idx] = val & 0x7f0;
-        break;
-
-      case ISA::IPR_DTB_ASN:
-        ipr[idx] = val & ULL(0xfe00000000000000);
-        break;
-
-      case ISA::IPR_EXC_SUM:
-      case ISA::IPR_EXC_MASK:
-        // any write to this register clears it
-        ipr[idx] = 0;
-        break;
-
-      case ISA::IPR_INTID:
-      case ISA::IPR_SL_RCV:
-      case ISA::IPR_MM_STAT:
-      case ISA::IPR_ITB_PTE_TEMP:
-      case ISA::IPR_DTB_PTE_TEMP:
-        // read-only registers
-        return Unimplemented_Opcode_Fault;
-
-      case ISA::IPR_HWINT_CLR:
-      case ISA::IPR_SL_XMIT:
-      case ISA::IPR_DC_FLUSH:
-      case ISA::IPR_IC_FLUSH:
-        // the following are write only
-        ipr[idx] = val;
-        break;
-
-      case ISA::IPR_DTB_IA:
-        // really a control write
-        ipr[idx] = 0;
-
-        cpu->dtb->flushAll();
-        break;
-
-      case ISA::IPR_DTB_IAP:
-        // really a control write
-        ipr[idx] = 0;
-
-        cpu->dtb->flushProcesses();
-        break;
-
-      case ISA::IPR_DTB_IS:
-        // really a control write
-        ipr[idx] = val;
-
-        cpu->dtb->flushAddr(val, DTB_ASN_ASN(ipr[ISA::IPR_DTB_ASN]));
-        break;
-
-      case ISA::IPR_DTB_TAG: {
-          struct ISA::PTE pte;
-
-          // FIXME: granularity hints NYI...
-          if (DTB_PTE_GH(ipr[ISA::IPR_DTB_PTE]) != 0)
-              panic("PTE GH field != 0");
-
-          // write entire quad
-          ipr[idx] = val;
-
-          // construct PTE for new entry
-          pte.ppn = DTB_PTE_PPN(ipr[ISA::IPR_DTB_PTE]);
-          pte.xre = DTB_PTE_XRE(ipr[ISA::IPR_DTB_PTE]);
-          pte.xwe = DTB_PTE_XWE(ipr[ISA::IPR_DTB_PTE]);
-          pte.fonr = DTB_PTE_FONR(ipr[ISA::IPR_DTB_PTE]);
-          pte.fonw = DTB_PTE_FONW(ipr[ISA::IPR_DTB_PTE]);
-          pte.asma = DTB_PTE_ASMA(ipr[ISA::IPR_DTB_PTE]);
-          pte.asn = DTB_ASN_ASN(ipr[ISA::IPR_DTB_ASN]);
-
-          // insert new TAG/PTE value into data TLB
-          cpu->dtb->insert(val, pte);
-      }
-        break;
-
-      case ISA::IPR_ITB_PTE: {
-          struct ISA::PTE pte;
-
-          // FIXME: granularity hints NYI...
-          if (ITB_PTE_GH(val) != 0)
-              panic("PTE GH field != 0");
-
-          // write entire quad
-          ipr[idx] = val;
-
-          // construct PTE for new entry
-          pte.ppn = ITB_PTE_PPN(val);
-          pte.xre = ITB_PTE_XRE(val);
-          pte.xwe = 0;
-          pte.fonr = ITB_PTE_FONR(val);
-          pte.fonw = ITB_PTE_FONW(val);
-          pte.asma = ITB_PTE_ASMA(val);
-          pte.asn = ITB_ASN_ASN(ipr[ISA::IPR_ITB_ASN]);
-
-          // insert new TAG/PTE value into data TLB
-          cpu->itb->insert(ipr[ISA::IPR_ITB_TAG], pte);
-      }
-        break;
-
-      case ISA::IPR_ITB_IA:
-        // really a control write
-        ipr[idx] = 0;
-
-        cpu->itb->flushAll();
-        break;
-
-      case ISA::IPR_ITB_IAP:
-        // really a control write
-        ipr[idx] = 0;
-
-        cpu->itb->flushProcesses();
-        break;
-
-      case ISA::IPR_ITB_IS:
-        // really a control write
-        ipr[idx] = val;
-
-        cpu->itb->flushAddr(val, ITB_ASN_ASN(ipr[ISA::IPR_ITB_ASN]));
-        break;
-
-      default:
-        // invalid IPR
-        return Unimplemented_Opcode_Fault;
-    }
-
-    // no error...
-    return No_Fault;
-}
-
-#endif // #if FULL_SYSTEM
-
 #endif // __CPU_O3_CPU_REGFILE_HH__
diff --git a/cpu/o3/rename.hh b/cpu/o3/rename.hh
index a17ec7311..07b442964 100644
--- a/cpu/o3/rename.hh
+++ b/cpu/o3/rename.hh
@@ -46,7 +46,6 @@ class SimpleRename
 {
   public:
     // Typedefs from the Impl.
-    typedef typename Impl::ISA ISA;
     typedef typename Impl::CPUPol CPUPol;
     typedef typename Impl::DynInstPtr DynInstPtr;
     typedef typename Impl::FullCPU FullCPU;
@@ -62,7 +61,7 @@ class SimpleRename
     typedef typename CPUPol::RenameMap RenameMap;
 
     // Typedefs from the ISA.
-    typedef typename ISA::Addr Addr;
+    typedef TheISA::RegIndex RegIndex;
 
   public:
     // Rename will block if ROB becomes full or issue queue becomes full,
diff --git a/cpu/o3/rename_map.hh b/cpu/o3/rename_map.hh
index c44c7a1ea..57be4a64a 100644
--- a/cpu/o3/rename_map.hh
+++ b/cpu/o3/rename_map.hh
@@ -38,9 +38,13 @@
 #include <vector>
 
 #include "cpu/o3/free_list.hh"
+//For RegIndex
+#include "arch/isa_traits.hh"
 
 class SimpleRenameMap
 {
+  protected:
+    typedef TheISA::RegIndex RegIndex;
   public:
     /**
      * Pair of a logical register and a physical register.  Tells the
diff --git a/cpu/o3/rob.hh b/cpu/o3/rob.hh
index 29ec48007..1185564ad 100644
--- a/cpu/o3/rob.hh
+++ b/cpu/o3/rob.hh
@@ -47,6 +47,8 @@
 template <class Impl>
 class ROB
 {
+  protected:
+    typedef TheISA::RegIndex RegIndex;
   public:
     //Typedefs from the Impl.
     typedef typename Impl::FullCPU FullCPU;
diff --git a/cpu/o3/store_set.hh b/cpu/o3/store_set.hh
index bcd590384..5a885d838 100644
--- a/cpu/o3/store_set.hh
+++ b/cpu/o3/store_set.hh
@@ -31,7 +31,7 @@
 
 #include <vector>
 
-#include "arch/alpha/isa_traits.hh"
+#include "arch/isa_traits.hh"
 #include "cpu/inst_seq.hh"
 
 class StoreSet
diff --git a/cpu/o3/tournament_pred.hh b/cpu/o3/tournament_pred.hh
index 58ea1a7d9..cb93c2f67 100644
--- a/cpu/o3/tournament_pred.hh
+++ b/cpu/o3/tournament_pred.hh
@@ -30,7 +30,7 @@
 #define __CPU_O3_CPU_TOURNAMENT_PRED_HH__
 
 // For Addr type.
-#include "arch/alpha/isa_traits.hh"
+#include "arch/isa_traits.hh"
 #include "cpu/o3/sat_counter.hh"
 
 class TournamentBP