merge

--HG--
extra : convert_revision : 47425264e672f727cbb13aa7b9bb2a67790b25e8

11 files changed, 38 insertions, 37 deletions

diff --git a/cpu/base_cpu.cc b/cpu/base_cpu.cc
index 74d2ceada..604ee335d 100644
--- a/cpu/base_cpu.cc
+++ b/cpu/base_cpu.cc
@@ -71,16 +71,16 @@ BaseCPU::BaseCPU(const string &_name, int _number_of_threads,
         maxThreadsPerCPU = number_of_threads;
 
     // allocate per-thread instruction-based event queues
-    comInsnEventQueue = new (EventQueue *)[number_of_threads];
+    comInstEventQueue = new (EventQueue *)[number_of_threads];
     for (int i = 0; i < number_of_threads; ++i)
-        comInsnEventQueue[i] = new EventQueue("instruction-based event queue");
+        comInstEventQueue[i] = new EventQueue("instruction-based event queue");
 
     //
     // set up instruction-count-based termination events, if any
     //
     if (max_insts_any_thread != 0)
         for (int i = 0; i < number_of_threads; ++i)
-            new SimExitEvent(comInsnEventQueue[i], max_insts_any_thread,
+            new SimExitEvent(comInstEventQueue[i], max_insts_any_thread,
                 "a thread reached the max instruction count");
 
     if (max_insts_all_threads != 0) {
@@ -90,7 +90,7 @@ BaseCPU::BaseCPU(const string &_name, int _number_of_threads,
         int *counter = new int;
         *counter = number_of_threads;
         for (int i = 0; i < number_of_threads; ++i)
-            new CountedExitEvent(comInsnEventQueue[i],
+            new CountedExitEvent(comInstEventQueue[i],
                 "all threads reached the max instruction count",
                 max_insts_all_threads, *counter);
     }
diff --git a/cpu/base_cpu.hh b/cpu/base_cpu.hh
index af1f34b67..648035732 100644
--- a/cpu/base_cpu.hh
+++ b/cpu/base_cpu.hh
@@ -128,7 +128,7 @@ class BaseCPU : public SimObject
      * scheduling events based on number of instructions committed by
      * a particular thread.
      */
-    EventQueue **comInsnEventQueue;
+    EventQueue **comInstEventQueue;
 
     /**
      * Vector of per-thread load-based event queues.  Used for
diff --git a/cpu/exec_context.cc b/cpu/exec_context.cc
index 23ae7eda8..6a5f463cd 100644
--- a/cpu/exec_context.cc
+++ b/cpu/exec_context.cc
@@ -51,7 +51,7 @@ ExecContext::ExecContext(BaseCPU *_cpu, int _thread_num, System *_sys,
 #ifdef FS_MEASURE
       swCtx(NULL),
 #endif
-      func_exe_insn(0), storeCondFailures(0)
+      func_exe_inst(0), storeCondFailures(0)
 {
     memset(&regs, 0, sizeof(RegFile));
 }
@@ -61,14 +61,14 @@ ExecContext::ExecContext(BaseCPU *_cpu, int _thread_num,
     : _status(ExecContext::Unallocated),
       cpu(_cpu), thread_num(_thread_num), cpu_id(-1),
       process(_process), mem(process->getMemory()), asid(_asid),
-      func_exe_insn(0), storeCondFailures(0)
+      func_exe_inst(0), storeCondFailures(0)
 {
 }
 
 ExecContext::ExecContext(BaseCPU *_cpu, int _thread_num,
                          FunctionalMemory *_mem, int _asid)
     : cpu(_cpu), thread_num(_thread_num), process(0), mem(_mem), asid(_asid),
-      func_exe_insn(0), storeCondFailures(0)
+      func_exe_inst(0), storeCondFailures(0)
 {
 }
 #endif
@@ -92,7 +92,7 @@ ExecContext::takeOverFrom(ExecContext *oldContext)
 #endif
     regs = oldContext->regs;
     cpu_id = oldContext->cpu_id;
-    func_exe_insn = oldContext->func_exe_insn;
+    func_exe_inst = oldContext->func_exe_inst;
 
     storeCondFailures = 0;
 
@@ -106,7 +106,7 @@ ExecContext::serialize(ostream &os)
     SERIALIZE_ENUM(_status);
     regs.serialize(os);
     // thread_num and cpu_id are deterministic from the config
-    SERIALIZE_SCALAR(func_exe_insn);
+    SERIALIZE_SCALAR(func_exe_inst);
 }
 
 
@@ -116,7 +116,7 @@ ExecContext::unserialize(Checkpoint *cp, const std::string &section)
     UNSERIALIZE_ENUM(_status);
     regs.unserialize(cp, section);
     // thread_num and cpu_id are deterministic from the config
-    UNSERIALIZE_SCALAR(func_exe_insn);
+    UNSERIALIZE_SCALAR(func_exe_inst);
 }
 
 
diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh
index f3c4b8015..e9dc5efec 100644
--- a/cpu/exec_context.hh
+++ b/cpu/exec_context.hh
@@ -158,7 +158,7 @@ class ExecContext
      * number of executed instructions, for matching with syscall trace
      * points in EIO files.
      */
-    Counter func_exe_insn;
+    Counter func_exe_inst;
 
     //
     // Count failed store conditionals so we can warn of apparent
@@ -189,17 +189,17 @@ class ExecContext
     int getInstAsid() { return ITB_ASN_ASN(regs.ipr[TheISA::IPR_ITB_ASN]); }
     int getDataAsid() { return DTB_ASN_ASN(regs.ipr[TheISA::IPR_DTB_ASN]); }
 
-    Fault translateInstReq(MemReqPtr req)
+    Fault translateInstReq(MemReqPtr &req)
     {
         return itb->translate(req);
     }
 
-    Fault translateDataReadReq(MemReqPtr req)
+    Fault translateDataReadReq(MemReqPtr &req)
     {
         return dtb->translate(req, false);
     }
 
-    Fault translateDataWriteReq(MemReqPtr req)
+    Fault translateDataWriteReq(MemReqPtr &req)
     {
         return dtb->translate(req, true);
     }
@@ -214,7 +214,7 @@ class ExecContext
     int getInstAsid() { return asid; }
     int getDataAsid() { return asid; }
 
-    Fault dummyTranslation(MemReqPtr req)
+    Fault dummyTranslation(MemReqPtr &req)
     {
 #if 0
         assert((req->vaddr >> 48 & 0xffff) == 0);
@@ -225,15 +225,15 @@ class ExecContext
         req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16;
         return No_Fault;
     }
-    Fault translateInstReq(MemReqPtr req)
+    Fault translateInstReq(MemReqPtr &req)
     {
         return dummyTranslation(req);
     }
-    Fault translateDataReadReq(MemReqPtr req)
+    Fault translateDataReadReq(MemReqPtr &req)
     {
         return dummyTranslation(req);
     }
-    Fault translateDataWriteReq(MemReqPtr req)
+    Fault translateDataWriteReq(MemReqPtr &req)
     {
         return dummyTranslation(req);
     }
@@ -241,7 +241,7 @@ class ExecContext
 #endif
 
     template <class T>
-    Fault read(MemReqPtr req, T& data)
+    Fault read(MemReqPtr &req, T &data)
     {
 #if defined(TARGET_ALPHA) && defined(FULL_SYSTEM)
         if (req->flags & LOCKED) {
@@ -254,7 +254,7 @@ class ExecContext
     }
 
     template <class T>
-    Fault write(MemReqPtr req, T& data)
+    Fault write(MemReqPtr &req, T &data)
     {
 #if defined(TARGET_ALPHA) && defined(FULL_SYSTEM)
 
diff --git a/cpu/exetrace.hh b/cpu/exetrace.hh
index d05dbe0cd..622ecd729 100644
--- a/cpu/exetrace.hh
+++ b/cpu/exetrace.hh
@@ -91,8 +91,9 @@ class InstRecord : public Record
     bool regs_valid;
 
   public:
-    InstRecord(Tick _cycle, BaseCPU *_cpu, StaticInstPtr<TheISA> _staticInst,
-               Addr _pc, bool spec, unsigned _thread)
+    InstRecord(Tick _cycle, BaseCPU *_cpu,
+               const StaticInstPtr<TheISA> &_staticInst,
+               Addr _pc, bool spec, int _thread)
         : Record(_cycle), cpu(_cpu), staticInst(_staticInst), PC(_pc),
           misspeculating(spec), thread(_thread)
     {
diff --git a/cpu/full_cpu/op_class.hh b/cpu/full_cpu/op_class.hh
index 67ccaabad..dbaa6624a 100644
--- a/cpu/full_cpu/op_class.hh
+++ b/cpu/full_cpu/op_class.hh
@@ -51,7 +51,6 @@ enum OpClass {
     FloatSQRT,		/* floating point square root */
     RdPort,		/* memory read port */
     WrPort,		/* memory write port */
-    LvqPort,		/* load value queue read port (redundant threading) */
     IPrefPort,
     Num_OpClasses	/* total functional unit classes */
 };
diff --git a/cpu/memtest/memtest.cc b/cpu/memtest/memtest.cc
index db24bb507..4ec5eed59 100644
--- a/cpu/memtest/memtest.cc
+++ b/cpu/memtest/memtest.cc
@@ -119,7 +119,7 @@ printData(ostream &os, uint8_t *data, int nbytes)
 }
 
 void
-MemTest::completeRequest(MemReqPtr req, uint8_t *data)
+MemTest::completeRequest(MemReqPtr &req, uint8_t *data)
 {
     switch (req->cmd) {
       case Read:
diff --git a/cpu/memtest/memtest.hh b/cpu/memtest/memtest.hh
index 3e7dff968..09f22a177 100644
--- a/cpu/memtest/memtest.hh
+++ b/cpu/memtest/memtest.hh
@@ -108,7 +108,7 @@ class MemTest : public BaseCPU
     Statistics::Scalar<> numCopies;
 
     // called by MemCompleteEvent::process()
-    void completeRequest(MemReqPtr req, uint8_t *data);
+    void completeRequest(MemReqPtr &req, uint8_t *data);
 
     friend class MemCompleteEvent;
 };
@@ -122,7 +122,7 @@ class MemCompleteEvent : public Event
 
   public:
 
-    MemCompleteEvent(MemReqPtr _req, uint8_t *_data, MemTest *_tester)
+    MemCompleteEvent(MemReqPtr &_req, uint8_t *_data, MemTest *_tester)
         : Event(&mainEventQueue),
           req(_req), data(_data), tester(_tester)
     {
diff --git a/cpu/simple_cpu/simple_cpu.cc b/cpu/simple_cpu/simple_cpu.cc
index 0d5fc4077..2e4dff280 100644
--- a/cpu/simple_cpu/simple_cpu.cc
+++ b/cpu/simple_cpu/simple_cpu.cc
@@ -321,7 +321,7 @@ change_thread_state(int thread_number, int activate, int priority)
 // precise architected memory state accessor macros
 template <class T>
 Fault
-SimpleCPU::read(Addr addr, T& data, unsigned flags)
+SimpleCPU::read(Addr addr, T &data, unsigned flags)
 {
     memReq->reset(addr, sizeof(T), flags);
 
@@ -653,7 +653,7 @@ SimpleCPU::tick()
         numInst++;
 
         // check for instruction-count-based events
-        comInsnEventQueue[0]->serviceEvents(numInst);
+        comInstEventQueue[0]->serviceEvents(numInst);
 
         // decode the instruction
         StaticInstPtr<TheISA> si(inst);
@@ -666,7 +666,7 @@ SimpleCPU::tick()
         xc->regs.ra = (inst >> 21) & 0x1f;
 #endif // FULL_SYSTEM
 
-        xc->func_exe_insn++;
+        xc->func_exe_inst++;
 
         fault = si->execute(this, xc, traceData);
 #ifdef FS_MEASURE
@@ -770,10 +770,10 @@ END_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
 BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
 
     INIT_PARAM_DFLT(max_insts_any_thread,
-                    "terminate when any thread reaches this insn count",
+                    "terminate when any thread reaches this inst count",
                     0),
     INIT_PARAM_DFLT(max_insts_all_threads,
-                    "terminate when all threads have reached this insn count",
+                    "terminate when all threads have reached this inst count",
                     0),
     INIT_PARAM_DFLT(max_loads_any_thread,
                     "terminate when any thread reaches this load count",
diff --git a/cpu/simple_cpu/simple_cpu.hh b/cpu/simple_cpu/simple_cpu.hh
index 7c9d4ea75..16753fa4f 100644
--- a/cpu/simple_cpu/simple_cpu.hh
+++ b/cpu/simple_cpu/simple_cpu.hh
@@ -227,7 +227,7 @@ class SimpleCPU : public BaseCPU
     virtual void unserialize(Checkpoint *cp, const std::string &section);
 
     template <class T>
-    Fault read(Addr addr, T& data, unsigned flags);
+    Fault read(Addr addr, T &data, unsigned flags);
 
     template <class T>
     Fault write(T data, Addr addr, unsigned flags,
diff --git a/cpu/static_inst.hh b/cpu/static_inst.hh
index 644c7dfc4..f3fd6fa24 100644
--- a/cpu/static_inst.hh
+++ b/cpu/static_inst.hh
@@ -312,10 +312,11 @@ class StaticInst : public StaticInstBase
     }
 
     /**
-     * Return the target address for an indirect branch (jump).
-     * The register value is read from the supplied execution context.
-     * Invalid if not an indirect branch (i.e. isIndirectCtrl()
-     * should be true).
+     * Return the target address for an indirect branch (jump).  The
+     * register value is read from the supplied execution context, so
+     * the result is valid only if the execution context is about to
+     * execute the branch in question.  Invalid if not an indirect
+     * branch (i.e. isIndirectCtrl() should be true).
      */
     virtual Addr branchTarget(ExecContext *xc)
     {