first pass at merging m5 with linux

--HG--
extra : convert_revision : dfe23349b80ae3b34d3cb95c5734e01ef62f700e

8 files changed, 90 insertions, 42 deletions

diff --git a/cpu/base_cpu.cc b/cpu/base_cpu.cc
index 73fb3e7fa..c6cff814d 100644
--- a/cpu/base_cpu.cc
+++ b/cpu/base_cpu.cc
@@ -237,10 +237,4 @@ BaseCPU::clear_interrupts()
 
 #endif // FULL_SYSTEM
 
-//
-// This declaration is not needed now that SamplingCPU provides a
-// BaseCPUBuilder object.
-//
-#if 0
 DEFINE_SIM_OBJECT_CLASS_NAME("BaseCPU", BaseCPU)
-#endif
diff --git a/cpu/exec_context.cc b/cpu/exec_context.cc
index eedd8b8a8..a89cf4bb5 100644
--- a/cpu/exec_context.cc
+++ b/cpu/exec_context.cc
@@ -42,7 +42,7 @@ using namespace std;
 // constructor
 #ifdef FULL_SYSTEM
 ExecContext::ExecContext(BaseCPU *_cpu, int _thread_num, System *_sys,
-                         AlphaItb *_itb, AlphaDtb *_dtb,
+                         AlphaITB *_itb, AlphaDTB *_dtb,
                          FunctionalMemory *_mem)
     : _status(ExecContext::Unallocated),
       kernelStats(this, _cpu), cpu(_cpu), thread_num(_thread_num),
@@ -60,6 +60,7 @@ ExecContext::ExecContext(BaseCPU *_cpu, int _thread_num,
       process(_process), mem(process->getMemory()), asid(_asid),
       func_exe_inst(0), storeCondFailures(0)
 {
+    memset(&regs, 0, sizeof(RegFile));
 }
 
 ExecContext::ExecContext(BaseCPU *_cpu, int _thread_num,
@@ -67,6 +68,7 @@ ExecContext::ExecContext(BaseCPU *_cpu, int _thread_num,
     : cpu(_cpu), thread_num(_thread_num), process(0), mem(_mem), asid(_asid),
       func_exe_inst(0), storeCondFailures(0)
 {
+    memset(&regs, 0, sizeof(RegFile));
 }
 #endif
 
diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh
index a72516ac7..7be83539a 100644
--- a/cpu/exec_context.hh
+++ b/cpu/exec_context.hh
@@ -124,8 +124,8 @@ class ExecContext
 #ifdef FULL_SYSTEM
 
     FunctionalMemory *mem;
-    AlphaItb *itb;
-    AlphaDtb *dtb;
+    AlphaITB *itb;
+    AlphaDTB *dtb;
     System *system;
 
     // the following two fields are redundant, since we can always
@@ -174,7 +174,7 @@ class ExecContext
     // constructor: initialize context from given process structure
 #ifdef FULL_SYSTEM
     ExecContext(BaseCPU *_cpu, int _thread_num, System *_system,
-                AlphaItb *_itb, AlphaDtb *_dtb, FunctionalMemory *_dem);
+                AlphaITB *_itb, AlphaDTB *_dtb, FunctionalMemory *_dem);
 #else
     ExecContext(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid);
     ExecContext(BaseCPU *_cpu, int _thread_num, FunctionalMemory *_mem,
@@ -387,7 +387,10 @@ class ExecContext
 #ifdef FULL_SYSTEM
     uint64_t readIpr(int idx, Fault &fault);
     Fault setIpr(int idx, uint64_t val);
+    int readIntrFlag() { return regs.intrflag; }
+    void setIntrFlag(int val) { regs.intrflag = val; }
     Fault hwrei();
+    bool inPalMode() { return PC_PAL(regs.pc); }
     void ev5_trap(Fault fault);
     bool simPalCheck(int palFunc);
 #endif
diff --git a/cpu/memtest/memtest.cc b/cpu/memtest/memtest.cc
index 051d9623a..5d608976d 100644
--- a/cpu/memtest/memtest.cc
+++ b/cpu/memtest/memtest.cc
@@ -40,7 +40,7 @@
 #include "mem/functional_mem/main_memory.hh"
 #include "sim/builder.hh"
 #include "sim/sim_events.hh"
-#include "sim/sim_stats.hh"
+#include "sim/stats.hh"
 
 using namespace std;
 
@@ -109,7 +109,6 @@ MemTest::MemTest(const string &name,
     // set up counters
     noResponseCycles = 0;
     numReads = 0;
-    numWrites = 0;
     tickEvent.schedule(0);
 }
 
@@ -142,21 +141,23 @@ MemTest::completeRequest(MemReqPtr &req, uint8_t *data)
         }
 
         numReads++;
+        numReadsStat++;
 
-        if (numReads.value() == nextProgressMessage) {
-            cerr << name() << ": completed " << numReads.value()
-                 << " read accesses @ " << curTick << endl;
+        if (numReads == nextProgressMessage) {
+            ccprintf(cerr, "%s: completed %d read accesses @%d\n",
+                     name(), numReads, curTick);
             nextProgressMessage += progressInterval;
         }
 
-        comLoadEventQueue[0]->serviceEvents(numReads.value());
+        comLoadEventQueue[0]->serviceEvents(numReads);
         break;
 
       case Write:
-        numWrites++;
+        numWritesStat++;
         break;
 
       case Copy:
+        numCopiesStat++;
         break;
 
       default:
@@ -187,17 +188,18 @@ MemTest::regStats()
 {
     using namespace Statistics;
 
-    numReads
+
+    numReadsStat
         .name(name() + ".num_reads")
         .desc("number of read accesses completed")
         ;
 
-    numWrites
+    numWritesStat
         .name(name() + ".num_writes")
         .desc("number of write accesses completed")
         ;
 
-    numCopies
+    numCopiesStat
         .name(name() + ".num_copies")
         .desc("number of copy accesses completed")
         ;
diff --git a/cpu/memtest/memtest.hh b/cpu/memtest/memtest.hh
index da6e180a0..f2409d54c 100644
--- a/cpu/memtest/memtest.hh
+++ b/cpu/memtest/memtest.hh
@@ -36,7 +36,7 @@
 #include "cpu/exec_context.hh"
 
 #include "base/statistics.hh"
-#include "sim/sim_stats.hh"
+#include "sim/stats.hh"
 
 class MemTest : public BaseCPU
 {
@@ -110,9 +110,10 @@ class MemTest : public BaseCPU
 
     Tick noResponseCycles;
 
-    Statistics::Scalar<> numReads;
-    Statistics::Scalar<> numWrites;
-    Statistics::Scalar<> numCopies;
+    uint64_t numReads;
+    Statistics::Scalar<> numReadsStat;
+    Statistics::Scalar<> numWritesStat;
+    Statistics::Scalar<> numCopiesStat;
 
     // called by MemCompleteEvent::process()
     void completeRequest(MemReqPtr &req, uint8_t *data);
diff --git a/cpu/simple_cpu/simple_cpu.cc b/cpu/simple_cpu/simple_cpu.cc
index c2796efd0..065140883 100644
--- a/cpu/simple_cpu/simple_cpu.cc
+++ b/cpu/simple_cpu/simple_cpu.cc
@@ -56,7 +56,7 @@
 #include "sim/host.hh"
 #include "sim/sim_events.hh"
 #include "sim/sim_object.hh"
-#include "sim/sim_stats.hh"
+#include "sim/stats.hh"
 
 #ifdef FULL_SYSTEM
 #include "base/remote_gdb.hh"
@@ -116,7 +116,7 @@ SimpleCPU::SimpleCPU(const string &_name,
                      Counter max_insts_all_threads,
                      Counter max_loads_any_thread,
                      Counter max_loads_all_threads,
-                     AlphaItb *itb, AlphaDtb *dtb,
+                     AlphaITB *itb, AlphaDTB *dtb,
                      FunctionalMemory *mem,
                      MemInterface *icache_interface,
                      MemInterface *dcache_interface,
@@ -714,7 +714,7 @@ SimpleCPU::tick()
 
         xc->func_exe_inst++;
 
-        fault = si->execute(this, xc, traceData);
+        fault = si->execute(this, traceData);
 
 #ifdef FULL_SYSTEM
         SWContext *ctx = xc->swCtx;
@@ -778,8 +778,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
     Param<Counter> max_loads_all_threads;
 
 #ifdef FULL_SYSTEM
-    SimObjectParam<AlphaItb *> itb;
-    SimObjectParam<AlphaDtb *> dtb;
+    SimObjectParam<AlphaITB *> itb;
+    SimObjectParam<AlphaDTB *> dtb;
     SimObjectParam<FunctionalMemory *> mem;
     SimObjectParam<System *> system;
     Param<int> mult;
@@ -852,11 +852,7 @@ CREATE_SIM_OBJECT(SimpleCPU)
                         defer_registration);
 
 #endif // FULL_SYSTEM
-#if 0
-    if (!defer_registration) {
-        cpu->registerExecContexts();
-    }
-#endif
+
     return cpu;
 }
 
diff --git a/cpu/simple_cpu/simple_cpu.hh b/cpu/simple_cpu/simple_cpu.hh
index 9edd66ab4..4977e6992 100644
--- a/cpu/simple_cpu/simple_cpu.hh
+++ b/cpu/simple_cpu/simple_cpu.hh
@@ -40,8 +40,8 @@
 #ifdef FULL_SYSTEM
 class Processor;
 class Kernel;
-class AlphaItb;
-class AlphaDtb;
+class AlphaITB;
+class AlphaDTB;
 class PhysicalMemory;
 
 class RemoteGDB;
@@ -131,7 +131,7 @@ class SimpleCPU : public BaseCPU
               System *_system,
               Counter max_insts_any_thread, Counter max_insts_all_threads,
               Counter max_loads_any_thread, Counter max_loads_all_threads,
-              AlphaItb *itb, AlphaDtb *dtb, FunctionalMemory *mem,
+              AlphaITB *itb, AlphaDTB *dtb, FunctionalMemory *mem,
               MemInterface *icache_interface, MemInterface *dcache_interface,
               bool _def_reg, Tick freq);
 
@@ -250,6 +250,56 @@ class SimpleCPU : public BaseCPU
     Fault copySrcTranslate(Addr src);
 
     Fault copy(Addr dest);
+
+    uint64_t readIntReg(int reg_idx) { return xc->readIntReg(reg_idx); }
+
+    float readFloatRegSingle(int reg_idx)
+    { return xc->readFloatRegSingle(reg_idx); }
+
+    double readFloatRegDouble(int reg_idx)
+    { return xc->readFloatRegDouble(reg_idx); }
+
+    uint64_t readFloatRegInt(int reg_idx)
+    { return xc->readFloatRegInt(reg_idx); }
+
+    void setIntReg(int reg_idx, uint64_t val)
+    { return xc->setIntReg(reg_idx, val); }
+
+    void setFloatRegSingle(int reg_idx, float val)
+    { return xc->setFloatRegSingle(reg_idx, val); }
+
+    void setFloatRegDouble(int reg_idx, double val)
+    { return xc->setFloatRegDouble(reg_idx, val); }
+
+    void setFloatRegInt(int reg_idx, uint64_t val)
+    { return xc->setFloatRegInt(reg_idx, val); }
+
+    uint64_t readPC() { return xc->readPC(); }
+    void setNextPC(uint64_t val) { return xc->setNextPC(val); }
+
+    uint64_t readUniq() { return xc->readUniq(); }
+    void setUniq(uint64_t val) { return xc->setUniq(val); }
+
+    uint64_t readFpcr() { return xc->readFpcr(); }
+    void setFpcr(uint64_t val) { return xc->setFpcr(val); }
+
+#ifdef FULL_SYSTEM
+    uint64_t readIpr(int idx, Fault &fault) { return xc->readIpr(idx, fault); }
+    Fault setIpr(int idx, uint64_t val) { return xc->setIpr(idx, val); }
+    Fault hwrei() { return xc->hwrei(); }
+    int readIntrFlag() { return xc->readIntrFlag(); }
+    void setIntrFlag(int val) { xc->setIntrFlag(val); }
+    bool inPalMode() { return xc->inPalMode(); }
+    void ev5_trap(Fault fault) { return xc->ev5_trap(fault); }
+    bool simPalCheck(int palFunc) { return xc->simPalCheck(palFunc); }
+#else
+    void syscall() { xc->syscall(); }
+#endif
+
+    bool misspeculating() { return xc->misspeculating(); }
+    ExecContext *xcBase() { return xc; }
 };
 
+typedef SimpleCPU SimpleCPUExecContext;
+
 #endif // __SIMPLE_CPU_HH__
diff --git a/cpu/static_inst.hh b/cpu/static_inst.hh
index cdf9aefa0..57208f8e6 100644
--- a/cpu/static_inst.hh
+++ b/cpu/static_inst.hh
@@ -41,10 +41,10 @@
 
 // forward declarations
 class ExecContext;
-class SpecExecContext;
-class SimpleCPU;
-class FullCPU;
 class DynInst;
+typedef DynInst FullCPUExecContext;
+class SimpleCPU;
+typedef SimpleCPU SimpleCPUExecContext;
 class SymbolTable;
 
 namespace Trace {
@@ -307,13 +307,13 @@ class StaticInst : public StaticInstBase
     /**
      * Execute this instruction under SimpleCPU model.
      */
-    virtual Fault execute(SimpleCPU *cpu, ExecContext *xc,
+    virtual Fault execute(SimpleCPUExecContext *xc,
                           Trace::InstRecord *traceData) = 0;
 
     /**
      * Execute this instruction under detailed FullCPU model.
      */
-    virtual Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
+    virtual Fault execute(FullCPUExecContext *xc,
                           Trace::InstRecord *traceData) = 0;
 
     /**