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| author | Ron Dreslinski <rdreslin@umich.edu> | 2005-04-29 21:01:43 -0400 |
|---|---|---|
| committer | Ron Dreslinski <rdreslin@umich.edu> | 2005-04-29 21:01:43 -0400 |
| commit | 602a489573c96d574798c622a70b1b466330fdaf (patch) | |
| tree | 4df5e972b36e13a647fe29f3054c8b8a10f4e524 /dev/ide_ctrl.cc | |
| parent | e07fee31cb7d3434d4ce5bb05a2a6b686f49fa50 (diff) | |
| download | gem5-602a489573c96d574798c622a70b1b466330fdaf.tar.xz | |
Add suport for no allocation of cache block on a dma read passing through a cache from the cpu-side interface
--HG--
extra : convert_revision : 0a3b3741924ed39c1c8710d0963e4c8f3e73f81a
Diffstat (limited to 'dev/ide_ctrl.cc')
| -rw-r--r-- | dev/ide_ctrl.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/dev/ide_ctrl.cc b/dev/ide_ctrl.cc index 857cdeb78..ae044427e 100644 --- a/dev/ide_ctrl.cc +++ b/dev/ide_ctrl.cc @@ -97,7 +97,8 @@ IdeController::IdeController(Params *p) dmaInterface = new DMAInterface<Bus>(name() + ".dma", params()->host_bus, - params()->host_bus, 1); + params()->host_bus, 1, + true); pioLatency = params()->pio_latency * params()->host_bus->clockRatio; } |