Major cleanup of python config code.

Special mpy importer is gone; everything is just plain
Python now (funky, but straight-up).
May not completely work yet... generates identical ini
files for many configs/kernel settings, but I have yet
to run it against regressions.  This commit is for my
own convenience and won't be pushed until more testing
is done.

python/m5/__init__.py:
    Get rid of mpy_importer and param_types.
python/m5/config.py:
    Major cleanup.  We now have separate classes and
    instances for SimObjects.  Proxy handling and param
    conversion significantly reorganized.  No explicit
    instantiation step anymore; we can dump an ini file
    straight from the original tree.
    Still needs more/better/truer comments.
test/genini.py:
    Replace LoadMpyFile() with built-in execfile().
    Export __main__.m5_build_env.
python/m5/objects/AlphaConsole.py:
python/m5/objects/AlphaFullCPU.py:
python/m5/objects/AlphaTLB.py:
python/m5/objects/BadDevice.py:
python/m5/objects/BaseCPU.py:
python/m5/objects/BaseCache.py:
python/m5/objects/BaseSystem.py:
python/m5/objects/Bus.py:
python/m5/objects/CoherenceProtocol.py:
python/m5/objects/Device.py:
python/m5/objects/DiskImage.py:
python/m5/objects/Ethernet.py:
python/m5/objects/Ide.py:
python/m5/objects/IntrControl.py:
python/m5/objects/MemTest.py:
python/m5/objects/Pci.py:
python/m5/objects/PhysicalMemory.py:
python/m5/objects/Platform.py:
python/m5/objects/Process.py:
python/m5/objects/Repl.py:
python/m5/objects/Root.py:
python/m5/objects/SimConsole.py:
python/m5/objects/SimpleDisk.py:
python/m5/objects/Tsunami.py:
python/m5/objects/Uart.py:
    Fixes for eliminating mpy_importer, and modified
    handling of frequency/latency params.
    Also renamed parent to Parent.

--HG--
rename : python/m5/objects/AlphaConsole.mpy => python/m5/objects/AlphaConsole.py
rename : python/m5/objects/AlphaFullCPU.mpy => python/m5/objects/AlphaFullCPU.py
rename : python/m5/objects/AlphaTLB.mpy => python/m5/objects/AlphaTLB.py
rename : python/m5/objects/BadDevice.mpy => python/m5/objects/BadDevice.py
rename : python/m5/objects/BaseCPU.mpy => python/m5/objects/BaseCPU.py
rename : python/m5/objects/BaseCache.mpy => python/m5/objects/BaseCache.py
rename : python/m5/objects/BaseSystem.mpy => python/m5/objects/BaseSystem.py
rename : python/m5/objects/Bus.mpy => python/m5/objects/Bus.py
rename : python/m5/objects/CoherenceProtocol.mpy => python/m5/objects/CoherenceProtocol.py
rename : python/m5/objects/Device.mpy => python/m5/objects/Device.py
rename : python/m5/objects/DiskImage.mpy => python/m5/objects/DiskImage.py
rename : python/m5/objects/Ethernet.mpy => python/m5/objects/Ethernet.py
rename : python/m5/objects/Ide.mpy => python/m5/objects/Ide.py
rename : python/m5/objects/IntrControl.mpy => python/m5/objects/IntrControl.py
rename : python/m5/objects/MemTest.mpy => python/m5/objects/MemTest.py
rename : python/m5/objects/Pci.mpy => python/m5/objects/Pci.py
rename : python/m5/objects/PhysicalMemory.mpy => python/m5/objects/PhysicalMemory.py
rename : python/m5/objects/Platform.mpy => python/m5/objects/Platform.py
rename : python/m5/objects/Process.mpy => python/m5/objects/Process.py
rename : python/m5/objects/Repl.mpy => python/m5/objects/Repl.py
rename : python/m5/objects/Root.mpy => python/m5/objects/Root.py
rename : python/m5/objects/SimConsole.mpy => python/m5/objects/SimConsole.py
rename : python/m5/objects/SimpleDisk.mpy => python/m5/objects/SimpleDisk.py
rename : python/m5/objects/Tsunami.mpy => python/m5/objects/Tsunami.py
rename : python/m5/objects/Uart.mpy => python/m5/objects/Uart.py
extra : convert_revision : 9dc55103a6f5b40eada4ed181a71a96fae6b0b76

32 files changed, 144 insertions, 114 deletions

diff --git a/python/m5/objects/AlphaConsole.mpy b/python/m5/objects/AlphaConsole.mpy
deleted file mode 100644
index 63aea5b7d..000000000
--- a/python/m5/objects/AlphaConsole.mpy
+++ /dev/null
@@ -1,9 +0,0 @@
-from Device import PioDevice
-
-simobj AlphaConsole(PioDevice):
-    type = 'AlphaConsole'
-    cpu = Param.BaseCPU(parent.any, "Processor")
-    disk = Param.SimpleDisk("Simple Disk")
-    num_cpus = Param.Int(1, "Number of CPUs")
-    sim_console = Param.SimConsole(parent.any, "The Simulator Console")
-    system = Param.BaseSystem(parent.any, "system object")
diff --git a/python/m5/objects/AlphaConsole.py b/python/m5/objects/AlphaConsole.py
new file mode 100644
index 000000000..9fe31b009
--- /dev/null
+++ b/python/m5/objects/AlphaConsole.py
@@ -0,0 +1,10 @@
+from m5 import *
+from Device import PioDevice
+
+class AlphaConsole(PioDevice):
+    type = 'AlphaConsole'
+    cpu = Param.BaseCPU(Parent.any, "Processor")
+    disk = Param.SimpleDisk("Simple Disk")
+    num_cpus = Param.Int(1, "Number of CPUs")
+    sim_console = Param.SimConsole(Parent.any, "The Simulator Console")
+    system = Param.BaseSystem(Parent.any, "system object")
diff --git a/python/m5/objects/AlphaFullCPU.mpy b/python/m5/objects/AlphaFullCPU.py
index bf3f2d718..48989d057 100644
--- a/python/m5/objects/AlphaFullCPU.mpy
+++ b/python/m5/objects/AlphaFullCPU.py
@@ -1,6 +1,7 @@
+from m5 import *
 from BaseCPU import BaseCPU
 
-simobj DerivAlphaFullCPU(BaseCPU):
+class DerivAlphaFullCPU(BaseCPU):
     type = 'DerivAlphaFullCPU'
 
     numThreads = Param.Unsigned("number of HW thread contexts")
diff --git a/python/m5/objects/AlphaTLB.mpy b/python/m5/objects/AlphaTLB.py
index 8e7cd62cc..5edf8e13d 100644
--- a/python/m5/objects/AlphaTLB.mpy
+++ b/python/m5/objects/AlphaTLB.py
@@ -1,12 +1,13 @@
-simobj AlphaTLB(SimObject):
+from m5 import *
+class AlphaTLB(SimObject):
     type = 'AlphaTLB'
     abstract = True
     size = Param.Int("TLB size")
 
-simobj AlphaDTB(AlphaTLB):
+class AlphaDTB(AlphaTLB):
     type = 'AlphaDTB'
     size = 64
 
-simobj AlphaITB(AlphaTLB):
+class AlphaITB(AlphaTLB):
     type = 'AlphaITB'
     size = 48
diff --git a/python/m5/objects/BadDevice.mpy b/python/m5/objects/BadDevice.py
index 35a12e0bf..3fba4637d 100644
--- a/python/m5/objects/BadDevice.mpy
+++ b/python/m5/objects/BadDevice.py
@@ -1,5 +1,6 @@
+from m5 import *
 from Device import PioDevice
 
-simobj BadDevice(PioDevice):
+class BadDevice(PioDevice):
     type = 'BadDevice'
     devicename = Param.String("Name of device to error on")
diff --git a/python/m5/objects/BaseCPU.mpy b/python/m5/objects/BaseCPU.py
index 707d1b94f..d4fa13d3b 100644
--- a/python/m5/objects/BaseCPU.mpy
+++ b/python/m5/objects/BaseCPU.py
@@ -1,4 +1,5 @@
-simobj BaseCPU(SimObject):
+from m5 import *
+class BaseCPU(SimObject):
     type = 'BaseCPU'
     abstract = True
     icache = Param.BaseMem(NULL, "L1 instruction cache object")
@@ -8,7 +9,7 @@ simobj BaseCPU(SimObject):
         dtb = Param.AlphaDTB("Data TLB")
         itb = Param.AlphaITB("Instruction TLB")
         mem = Param.FunctionalMemory("memory")
-        system = Param.BaseSystem(parent.any, "system object")
+        system = Param.BaseSystem(Parent.any, "system object")
     else:
         workload = VectorParam.Process("processes to run")
 
@@ -24,4 +25,4 @@ simobj BaseCPU(SimObject):
     defer_registration = Param.Bool(False,
         "defer registration with system (for sampling)")
 
-    cycle_time = Param.ClockPeriod(parent.frequency, "clock speed")
+    cycle_time = Param.Latency(Parent.frequency.latency, "clock speed")
diff --git a/python/m5/objects/BaseCache.mpy b/python/m5/objects/BaseCache.py
index a9a665f77..d311969fa 100644
--- a/python/m5/objects/BaseCache.mpy
+++ b/python/m5/objects/BaseCache.py
@@ -1,8 +1,9 @@
+from m5 import *
 from BaseMem import BaseMem
 
 class Prefetch(Enum): vals = ['none', 'tagged', 'stride', 'ghb']
 
-simobj BaseCache(BaseMem):
+class BaseCache(BaseMem):
     type = 'BaseCache'
     adaptive_compression = Param.Bool(False,
         "Use an adaptive compression scheme")
@@ -10,7 +11,7 @@ simobj BaseCache(BaseMem):
     block_size = Param.Int("block size in bytes")
     compressed_bus = Param.Bool(False,
         "This cache connects to a compressed memory")
-    compression_latency = Param.Latency('0c',
+    compression_latency = Param.Latency(0,
         "Latency in cycles of compression algorithm")
     do_copy = Param.Bool(False, "perform fast copies in the cache")
     hash_delay = Param.Int(1, "time in cycles of hash access")
diff --git a/python/m5/objects/BaseSystem.mpy b/python/m5/objects/BaseSystem.py
index 29fe3e1d9..48c70e44f 100644
--- a/python/m5/objects/BaseSystem.mpy
+++ b/python/m5/objects/BaseSystem.py
@@ -1,10 +1,11 @@
-simobj BaseSystem(SimObject):
+from m5 import *
+class BaseSystem(SimObject):
     type = 'BaseSystem'
     abstract = True
-    boot_cpu_frequency = Param.ClockPeriod(parent.cpu[0].cycle_time,
-        "Boot Processor Frequency")
-    memctrl = Param.MemoryController(parent.any, "memory controller")
-    physmem = Param.PhysicalMemory(parent.any, "phsyical memory")
+    boot_cpu_frequency = Param.Frequency(Self.cpu[0].cycle_time.frequency,
+                                         "boot processor frequency")
+    memctrl = Param.MemoryController(Parent.any, "memory controller")
+    physmem = Param.PhysicalMemory(Parent.any, "phsyical memory")
     kernel = Param.String("file that contains the kernel code")
     console = Param.String("file that contains the console code")
     pal = Param.String("file that contains palcode")
diff --git a/python/m5/objects/Bus.mpy b/python/m5/objects/Bus.mpy
deleted file mode 100644
index aa12f757a..000000000
--- a/python/m5/objects/Bus.mpy
+++ /dev/null
@@ -1,6 +0,0 @@
-from BaseHier import BaseHier
-
-simobj Bus(BaseHier):
-    type = 'Bus'
-    clock_ratio = Param.ClockPeriod("ratio of CPU to bus frequency")
-    width = Param.Int("bus width in bytes")
diff --git a/python/m5/objects/Bus.py b/python/m5/objects/Bus.py
new file mode 100644
index 000000000..1ed87d2e7
--- /dev/null
+++ b/python/m5/objects/Bus.py
@@ -0,0 +1,7 @@
+from m5 import *
+from BaseHier import BaseHier
+
+class Bus(BaseHier):
+    type = 'Bus'
+    clock_ratio = Param.Frequency("ratio of CPU to bus frequency")
+    width = Param.Int("bus width in bytes")
diff --git a/python/m5/objects/CoherenceProtocol.mpy b/python/m5/objects/CoherenceProtocol.py
index f3b0026b7..7013000d6 100644
--- a/python/m5/objects/CoherenceProtocol.mpy
+++ b/python/m5/objects/CoherenceProtocol.py
@@ -1,6 +1,7 @@
+from m5 import *
 class Coherence(Enum): vals = ['uni', 'msi', 'mesi', 'mosi', 'moesi']
 
-simobj CoherenceProtocol(SimObject):
+class CoherenceProtocol(SimObject):
     type = 'CoherenceProtocol'
     do_upgrades = Param.Bool(True, "use upgrade transactions?")
     protocol = Param.Coherence("name of coherence protocol")
diff --git a/python/m5/objects/Device.mpy b/python/m5/objects/Device.py
index a0d02a647..7f6ccd3e7 100644
--- a/python/m5/objects/Device.mpy
+++ b/python/m5/objects/Device.py
@@ -1,3 +1,4 @@
+from m5 import *
 from FunctionalMemory import FunctionalMemory
 
 # This device exists only because there are some devices that I don't
@@ -10,24 +11,24 @@ from FunctionalMemory import FunctionalMemory
 # some further configuration must be done, it must be done during the
 # initialization phase at which point all SimObject pointers will be
 # valid.
-simobj FooPioDevice(FunctionalMemory):
+class FooPioDevice(FunctionalMemory):
     type = 'PioDevice'
     abstract = True
     addr = Param.Addr("Device Address")
-    mmu = Param.MemoryController(parent.any, "Memory Controller")
+    mmu = Param.MemoryController(Parent.any, "Memory Controller")
     io_bus = Param.Bus(NULL, "The IO Bus to attach to")
     pio_latency = Param.Tick(1, "Programmed IO latency in bus cycles")
 
-simobj FooDmaDevice(FooPioDevice):
+class FooDmaDevice(FooPioDevice):
     type = 'DmaDevice'
     abstract = True
 
-simobj PioDevice(FooPioDevice):
+class PioDevice(FooPioDevice):
     type = 'PioDevice'
     abstract = True
-    platform = Param.Platform(parent.any, "Platform")
+    platform = Param.Platform(Parent.any, "Platform")
 
-simobj DmaDevice(PioDevice):
+class DmaDevice(PioDevice):
     type = 'DmaDevice'
     abstract = True
 
diff --git a/python/m5/objects/DiskImage.mpy b/python/m5/objects/DiskImage.py
index 80ef7b072..0d55e9329 100644
--- a/python/m5/objects/DiskImage.mpy
+++ b/python/m5/objects/DiskImage.py
@@ -1,13 +1,14 @@
-simobj DiskImage(SimObject):
+from m5 import *
+class DiskImage(SimObject):
     type = 'DiskImage'
     abstract = True
     image_file = Param.String("disk image file")
     read_only = Param.Bool(False, "read only image")
 
-simobj RawDiskImage(DiskImage):
+class RawDiskImage(DiskImage):
     type = 'RawDiskImage'
 
-simobj CowDiskImage(DiskImage):
+class CowDiskImage(DiskImage):
     type = 'CowDiskImage'
     child = Param.DiskImage("child image")
     table_size = Param.Int(65536, "initial table size")
diff --git a/python/m5/objects/Ethernet.mpy b/python/m5/objects/Ethernet.py
index 0065a238f..69dec1528 100644
--- a/python/m5/objects/Ethernet.mpy
+++ b/python/m5/objects/Ethernet.py
@@ -1,12 +1,13 @@
+from m5 import *
 from Device import DmaDevice
 from Pci import PciDevice
 
-simobj EtherInt(SimObject):
+class EtherInt(SimObject):
     type = 'EtherInt'
     abstract = True
     peer = Param.EtherInt(NULL, "peer interface")
 
-simobj EtherLink(SimObject):
+class EtherLink(SimObject):
     type = 'EtherLink'
     int1 = Param.EtherInt("interface 1")
     int2 = Param.EtherInt("interface 2")
@@ -14,23 +15,23 @@ simobj EtherLink(SimObject):
     speed = Param.NetworkBandwidth('100Mbps', "link speed")
     dump = Param.EtherDump(NULL, "dump object")
 
-simobj EtherBus(SimObject):
+class EtherBus(SimObject):
     type = 'EtherBus'
     loopback = Param.Bool(True, "send packet back to the sending interface")
     dump = Param.EtherDump(NULL, "dump object")
     speed = Param.NetworkBandwidth('100Mbps', "bus speed in bits per second")
 
-simobj EtherTap(EtherInt):
+class EtherTap(EtherInt):
     type = 'EtherTap'
     bufsz = Param.Int(10000, "tap buffer size")
     dump = Param.EtherDump(NULL, "dump object")
     port = Param.UInt16(3500, "tap port")
 
-simobj EtherDump(SimObject):
+class EtherDump(SimObject):
     type = 'EtherDump'
     file = Param.String("dump file")
 
-simobj EtherDev(DmaDevice):
+class EtherDev(DmaDevice):
     type = 'EtherDev'
     hardware_address = Param.EthernetAddr(NextEthernetAddr,
         "Ethernet Hardware Address")
@@ -49,10 +50,10 @@ simobj EtherDev(DmaDevice):
 
     intr_delay = Param.Latency('0us', "Interrupt Delay")
     payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload")
-    physmem = Param.PhysicalMemory(parent.any, "Physical Memory")
-    tlaser = Param.Turbolaser(parent.any, "Turbolaser")
+    physmem = Param.PhysicalMemory(Parent.any, "Physical Memory")
+    tlaser = Param.Turbolaser(Parent.any, "Turbolaser")
 
-simobj NSGigE(PciDevice):
+class NSGigE(PciDevice):
     type = 'NSGigE'
     hardware_address = Param.EthernetAddr(NextEthernetAddr,
         "Ethernet Hardware Address")
@@ -79,17 +80,17 @@ simobj NSGigE(PciDevice):
 
     intr_delay = Param.Latency('0us', "Interrupt Delay in microseconds")
     payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload")
-    physmem = Param.PhysicalMemory(parent.any, "Physical Memory")
+    physmem = Param.PhysicalMemory(Parent.any, "Physical Memory")
 
-simobj EtherDevInt(EtherInt):
+class EtherDevInt(EtherInt):
     type = 'EtherDevInt'
     device = Param.EtherDev("Ethernet device of this interface")
 
-simobj NSGigEInt(EtherInt):
+class NSGigEInt(EtherInt):
     type = 'NSGigEInt'
     device = Param.NSGigE("Ethernet device of this interface")
 
-simobj Sinic(PciDevice):
+class Sinic(PciDevice):
     type = 'Sinic'
     hardware_address = Param.EthernetAddr(NextEthernetAddr,
         "Ethernet Hardware Address")
@@ -114,8 +115,8 @@ simobj Sinic(PciDevice):
 
     intr_delay = Param.Latency('0us', "Interrupt Delay in microseconds")
     payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload")
-    physmem = Param.PhysicalMemory(parent.any, "Physical Memory")
+    physmem = Param.PhysicalMemory(Parent.any, "Physical Memory")
 
-simobj SinicInt(EtherInt):
+class SinicInt(EtherInt):
     type = 'SinicInt'
     device = Param.Sinic("Ethernet device of this interface")
diff --git a/python/m5/objects/Ide.mpy b/python/m5/objects/Ide.py
index 02b1d9567..6855ec653 100644
--- a/python/m5/objects/Ide.mpy
+++ b/python/m5/objects/Ide.py
@@ -1,14 +1,15 @@
+from m5 import *
 from Pci import PciDevice
 
 class IdeID(Enum): vals = ['master', 'slave']
 
-simobj IdeDisk(SimObject):
+class IdeDisk(SimObject):
     type = 'IdeDisk'
     delay = Param.Latency('1us', "Fixed disk delay in microseconds")
     driveID = Param.IdeID('master', "Drive ID")
     image = Param.DiskImage("Disk image")
-    physmem = Param.PhysicalMemory(parent.any, "Physical memory")
+    physmem = Param.PhysicalMemory(Parent.any, "Physical memory")
 
-simobj IdeController(PciDevice):
+class IdeController(PciDevice):
     type = 'IdeController'
     disks = VectorParam.IdeDisk("IDE disks attached to this controller")
diff --git a/python/m5/objects/IntrControl.mpy b/python/m5/objects/IntrControl.mpy
deleted file mode 100644
index 144be0fd4..000000000
--- a/python/m5/objects/IntrControl.mpy
+++ /dev/null
@@ -1,3 +0,0 @@
-simobj IntrControl(SimObject):
-    type = 'IntrControl'
-    cpu = Param.BaseCPU(parent.any, "the cpu")
diff --git a/python/m5/objects/IntrControl.py b/python/m5/objects/IntrControl.py
new file mode 100644
index 000000000..66c82c182
--- /dev/null
+++ b/python/m5/objects/IntrControl.py
@@ -0,0 +1,4 @@
+from m5 import *
+class IntrControl(SimObject):
+    type = 'IntrControl'
+    cpu = Param.BaseCPU(Parent.any, "the cpu")
diff --git a/python/m5/objects/MemTest.mpy b/python/m5/objects/MemTest.py
index af14ed9c3..34299faf0 100644
--- a/python/m5/objects/MemTest.mpy
+++ b/python/m5/objects/MemTest.py
@@ -1,4 +1,5 @@
-simobj MemTest(SimObject):
+from m5 import *
+class MemTest(SimObject):
     type = 'MemTest'
     cache = Param.BaseCache("L1 cache")
     check_mem = Param.FunctionalMemory("check memory")
diff --git a/python/m5/objects/Pci.mpy b/python/m5/objects/Pci.py
index b9b3e5a95..0957e2883 100644
--- a/python/m5/objects/Pci.mpy
+++ b/python/m5/objects/Pci.py
@@ -1,6 +1,7 @@
+from m5 import *
 from Device import FooPioDevice, DmaDevice
 
-simobj PciConfigData(SimObject):
+class PciConfigData(SimObject):
     type = 'PciConfigData'
     VendorID = Param.UInt16("Vendor ID")
     DeviceID = Param.UInt16("Device ID")
@@ -37,15 +38,15 @@ simobj PciConfigData(SimObject):
     MaximumLatency = Param.UInt8(0x00, "Maximum Latency")
     MinimumGrant = Param.UInt8(0x00, "Minimum Grant")
 
-simobj PciConfigAll(FooPioDevice):
+class PciConfigAll(FooPioDevice):
     type = 'PciConfigAll'
 
-simobj PciDevice(DmaDevice):
+class PciDevice(DmaDevice):
     type = 'PciDevice'
     abstract = True
     addr = 0xffffffffL
     pci_bus = Param.Int("PCI bus")
     pci_dev = Param.Int("PCI device number")
     pci_func = Param.Int("PCI function code")
-    configdata = Param.PciConfigData(parent.any, "PCI Config data")
-    configspace = Param.PciConfigAll(parent.any, "PCI Configspace")
+    configdata = Param.PciConfigData(Parent.any, "PCI Config data")
+    configspace = Param.PciConfigAll(Parent.any, "PCI Configspace")
diff --git a/python/m5/objects/PhysicalMemory.mpy b/python/m5/objects/PhysicalMemory.py
index e6df2a161..f50937ee6 100644
--- a/python/m5/objects/PhysicalMemory.mpy
+++ b/python/m5/objects/PhysicalMemory.py
@@ -1,7 +1,8 @@
+from m5 import *
 from FunctionalMemory import FunctionalMemory
 
-simobj PhysicalMemory(FunctionalMemory):
+class PhysicalMemory(FunctionalMemory):
     type = 'PhysicalMemory'
     range = Param.AddrRange("Device Address")
     file = Param.String('', "memory mapped file")
-    mmu = Param.MemoryController(parent.any, "Memory Controller")
+    mmu = Param.MemoryController(Parent.any, "Memory Controller")
diff --git a/python/m5/objects/Platform.mpy b/python/m5/objects/Platform.mpy
deleted file mode 100644
index 166f3f4a1..000000000
--- a/python/m5/objects/Platform.mpy
+++ /dev/null
@@ -1,4 +0,0 @@
-simobj Platform(SimObject):
-    type = 'Platform'
-    abstract = True
-    intrctrl = Param.IntrControl(parent.any, "interrupt controller")
diff --git a/python/m5/objects/Platform.py b/python/m5/objects/Platform.py
new file mode 100644
index 000000000..4da0ffab4
--- /dev/null
+++ b/python/m5/objects/Platform.py
@@ -0,0 +1,5 @@
+from m5 import *
+class Platform(SimObject):
+    type = 'Platform'
+    abstract = True
+    intrctrl = Param.IntrControl(Parent.any, "interrupt controller")
diff --git a/python/m5/objects/Process.mpy b/python/m5/objects/Process.py
index 6a91c09c2..17a66c6d9 100644
--- a/python/m5/objects/Process.mpy
+++ b/python/m5/objects/Process.py
@@ -1,15 +1,16 @@
-simobj Process(SimObject):
+from m5 import *
+class Process(SimObject):
     type = 'Process'
     abstract = True
     output = Param.String('cout', 'filename for stdout/stderr')
 
-simobj LiveProcess(Process):
+class LiveProcess(Process):
     type = 'LiveProcess'
     cmd = VectorParam.String("command line (executable plus arguments)")
     env = VectorParam.String('', "environment settings")
     input = Param.String('cin', "filename for stdin")
 
-simobj EioProcess(Process):
+class EioProcess(Process):
     type = 'EioProcess'
     chkpt = Param.String('', "EIO checkpoint file name (optional)")
     file = Param.String("EIO trace file name")
diff --git a/python/m5/objects/Repl.mpy b/python/m5/objects/Repl.py
index fff5a2a02..afd256082 100644
--- a/python/m5/objects/Repl.mpy
+++ b/python/m5/objects/Repl.py
@@ -1,8 +1,9 @@
-simobj Repl(SimObject):
+from m5 import *
+class Repl(SimObject):
     type = 'Repl'
     abstract = True
 
-simobj GenRepl(Repl):
+class GenRepl(Repl):
     type = 'GenRepl'
     fresh_res = Param.Int("associativity")
     num_pools = Param.Int("capacity in bytes")
diff --git a/python/m5/objects/Root.mpy b/python/m5/objects/Root.mpy
deleted file mode 100644
index 2493dc4ff..000000000
--- a/python/m5/objects/Root.mpy
+++ /dev/null
@@ -1,14 +0,0 @@
-from HierParams import HierParams
-from Serialize import Serialize
-from Statistics import Statistics
-from Trace import Trace
-
-simobj Root(SimObject):
-    type = 'Root'
-    frequency = Param.RootFrequency('200MHz', "tick frequency")
-    output_file = Param.String('cout', "file to dump simulator output to")
-    hier = HierParams(do_data = False, do_events = True)
-    checkpoint = Param.String('', "Checkpoint file")
-    stats = Statistics()
-    trace = Trace()
-    serialize = Serialize()
diff --git a/python/m5/objects/Root.py b/python/m5/objects/Root.py
new file mode 100644
index 000000000..78d5388f0
--- /dev/null
+++ b/python/m5/objects/Root.py
@@ -0,0 +1,20 @@
+from m5 import *
+from HierParams import HierParams
+from Serialize import Serialize
+from Statistics import Statistics
+from Trace import Trace
+
+class Root(SimObject):
+    type = 'Root'
+    frequency = Param.RootFrequency('200MHz', "tick frequency")
+    output_file = Param.String('cout', "file to dump simulator output to")
+    checkpoint = Param.String('', "checkpoint file to load")
+#    hier = Param.HierParams(HierParams(do_data = False, do_events = True),
+#                            "shared memory hierarchy parameters")
+#    stats = Param.Statistics(Statistics(), "statistics object")
+#    trace = Param.Trace(Trace(), "trace object")
+#    serialize = Param.Serialize(Serialize(), "checkpoint generation options")
+    hier = HierParams(do_data = False, do_events = True)
+    stats = Statistics()
+    trace = Trace()
+    serialize = Serialize()
diff --git a/python/m5/objects/SimConsole.mpy b/python/m5/objects/SimConsole.py
index 53ddaa25c..df3061908 100644
--- a/python/m5/objects/SimConsole.mpy
+++ b/python/m5/objects/SimConsole.py
@@ -1,11 +1,12 @@
-simobj ConsoleListener(SimObject):
+from m5 import *
+class ConsoleListener(SimObject):
     type = 'ConsoleListener'
     port = Param.TcpPort(3456, "listen port")
 
-simobj SimConsole(SimObject):
+class SimConsole(SimObject):
     type = 'SimConsole'
     append_name = Param.Bool(True, "append name() to filename")
-    intr_control = Param.IntrControl(parent.any, "interrupt controller")
+    intr_control = Param.IntrControl(Parent.any, "interrupt controller")
     listener = Param.ConsoleListener("console listener")
     number = Param.Int(0, "console number")
     output = Param.String('console', "file to dump output to")
diff --git a/python/m5/objects/SimpleDisk.mpy b/python/m5/objects/SimpleDisk.mpy
deleted file mode 100644
index b616fb3d1..000000000
--- a/python/m5/objects/SimpleDisk.mpy
+++ /dev/null
@@ -1,4 +0,0 @@
-simobj SimpleDisk(SimObject):
-    type = 'SimpleDisk'
-    disk = Param.DiskImage("Disk Image")
-    physmem = Param.PhysicalMemory(parent.any, "Physical Memory")
diff --git a/python/m5/objects/SimpleDisk.py b/python/m5/objects/SimpleDisk.py
new file mode 100644
index 000000000..48448e6e5
--- /dev/null
+++ b/python/m5/objects/SimpleDisk.py
@@ -0,0 +1,5 @@
+from m5 import *
+class SimpleDisk(SimObject):
+    type = 'SimpleDisk'
+    disk = Param.DiskImage("Disk Image")
+    physmem = Param.PhysicalMemory(Parent.any, "Physical Memory")
diff --git a/python/m5/objects/Tsunami.mpy b/python/m5/objects/Tsunami.py
index c17eae121..fa3c18127 100644
--- a/python/m5/objects/Tsunami.mpy
+++ b/python/m5/objects/Tsunami.py
@@ -1,25 +1,26 @@
+from m5 import *
 from Device import FooPioDevice
 from Platform import Platform
 
-simobj Tsunami(Platform):
+class Tsunami(Platform):
     type = 'Tsunami'
     pciconfig = Param.PciConfigAll("PCI configuration")
-    system = Param.BaseSystem(parent.any, "system")
+    system = Param.BaseSystem(Parent.any, "system")
 
-simobj TsunamiCChip(FooPioDevice):
+class TsunamiCChip(FooPioDevice):
     type = 'TsunamiCChip'
-    tsunami = Param.Tsunami(parent.any, "Tsunami")
+    tsunami = Param.Tsunami(Parent.any, "Tsunami")
 
-simobj TsunamiFake(FooPioDevice):
+class TsunamiFake(FooPioDevice):
     type = 'TsunamiFake'
 
-simobj TsunamiIO(FooPioDevice):
+class TsunamiIO(FooPioDevice):
     type = 'TsunamiIO'
     time = Param.UInt64(1136073600,
         "System time to use (0 for actual time, default is 1/1/06)")
-    tsunami = Param.Tsunami(parent.any, "Tsunami")
+    tsunami = Param.Tsunami(Parent.any, "Tsunami")
     frequency = Param.Frequency('1024Hz', "frequency of interrupts")
 
-simobj TsunamiPChip(FooPioDevice):
+class TsunamiPChip(FooPioDevice):
     type = 'TsunamiPChip'
-    tsunami = Param.Tsunami(parent.any, "Tsunami")
+    tsunami = Param.Tsunami(Parent.any, "Tsunami")
diff --git a/python/m5/objects/Uart.mpy b/python/m5/objects/Uart.mpy
deleted file mode 100644
index 5a6c25f8e..000000000
--- a/python/m5/objects/Uart.mpy
+++ /dev/null
@@ -1,6 +0,0 @@
-from Device import PioDevice
-
-simobj Uart(PioDevice):
-    type = 'Uart'
-    console = Param.SimConsole(parent.any, "The console")
-    size = Param.Addr(0x8, "Device size")
diff --git a/python/m5/objects/Uart.py b/python/m5/objects/Uart.py
new file mode 100644
index 000000000..cfb09acad
--- /dev/null
+++ b/python/m5/objects/Uart.py
@@ -0,0 +1,7 @@
+from m5 import *
+from Device import PioDevice
+
+class Uart(PioDevice):
+    type = 'Uart'
+    console = Param.SimConsole(Parent.any, "The console")
+    size = Param.Addr(0x8, "Device size")