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| author | Ron Dreslinski <rdreslin@umich.edu> | 2005-04-29 21:01:43 -0400 |
|---|---|---|
| committer | Ron Dreslinski <rdreslin@umich.edu> | 2005-04-29 21:01:43 -0400 |
| commit | 602a489573c96d574798c622a70b1b466330fdaf (patch) | |
| tree | 4df5e972b36e13a647fe29f3054c8b8a10f4e524 /python/m5/objects | |
| parent | e07fee31cb7d3434d4ce5bb05a2a6b686f49fa50 (diff) | |
| download | gem5-602a489573c96d574798c622a70b1b466330fdaf.tar.xz | |
Add suport for no allocation of cache block on a dma read passing through a cache from the cpu-side interface
--HG--
extra : convert_revision : 0a3b3741924ed39c1c8710d0963e4c8f3e73f81a
Diffstat (limited to 'python/m5/objects')
| -rw-r--r-- | python/m5/objects/Ethernet.mpy | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/python/m5/objects/Ethernet.mpy b/python/m5/objects/Ethernet.mpy index 7cc58421a..141d138da 100644 --- a/python/m5/objects/Ethernet.mpy +++ b/python/m5/objects/Ethernet.mpy @@ -41,6 +41,7 @@ simobj EtherDev(DmaDevice): dma_read_factor = Param.Latency('0us', "multiplier for dma reads") dma_write_delay = Param.Latency('0us', "fixed delay for dma writes") dma_write_factor = Param.Latency('0us', "multiplier for dma writes") + dma_no_allocate = Param.Bool(True, "Should we allocate cache on read") rx_filter = Param.Bool(True, "Enable Receive Filter") rx_delay = Param.Latency('1us', "Receive Delay") @@ -64,6 +65,8 @@ simobj NSGigE(PciDevice): dma_read_factor = Param.Latency('0us', "multiplier for dma reads") dma_write_delay = Param.Latency('0us', "fixed delay for dma writes") dma_write_factor = Param.Latency('0us', "multiplier for dma writes") + dma_no_allocate = Param.Bool(True, "Should we allocate cache on read") + rx_filter = Param.Bool(True, "Enable Receive Filter") rx_delay = Param.Latency('1us', "Receive Delay") |