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AgeCommit message (Expand)Author
2006-05-22New directory structure:Steve Reinhardt
2006-05-17Get basic full-system working with AtomicSimpleCPU.Steve Reinhardt
2006-05-16Split SimpleCPU into two different models, AtomicSimpleCPU andSteve Reinhardt
2006-05-12Merge zeep.pool:/z/saidi/work/m5.headAli Saidi
2006-04-28random mix of tidbitsAli Saidi
2006-04-28add a bridge object, modify bus object to be able to connect to other buses o...Ali Saidi
2006-04-26Major update to sinic to support VSINIC betterNathan Binkert
2006-04-24Mostly done with all device models for new memory system. Still need to get t...Ali Saidi
2006-04-20make ide disk work for newmemAli Saidi
2006-04-11fullsys now builds and runs for about one cycleAli Saidi
2006-04-06fixes for newmemAli Saidi
2006-03-26Add the bus and connector objects to sconsAli Saidi
2006-03-25Implement a very very simple busAli Saidi
2006-03-15add translations for new sections that are mmapped or when the brkAli Saidi
2006-03-10Compiles now (with CPU_MODELS=SimpleCPU), but hangsSteve Reinhardt
2006-03-09Hand merge. Stuff probably doesn't compile.Gabe Black
2006-03-04move alpha specific code into arch/alphaAli Saidi
2006-03-03Ethernet devices have an RSS option to tell the driver toNathan Binkert
2006-03-01More progress toward actually running a program.Steve Reinhardt
2006-02-27Fixes so that it compiles properly. Still working on .py file issues.Ron Dreslinski
2006-02-23Add support for multiple ports on the memory. Hook up simple cpu to memory.Ron Dreslinski
2006-02-23Update functional memory to have a response eventRon Dreslinski
2006-02-20Get rid of the code that delays PIO write accessesNathan Binkert
2006-01-28Changes for Process object initialization in merged-memory environment.Steve Reinhardt
2005-11-25Virtualize sinicNathan Binkert
2005-11-21add support for delaying pio writes until the cache access occursNathan Binkert
2005-11-21BARs now of type MemorySize32Nathan Binkert
2005-11-20io_bus is split out into pio_bus and dma_bus so that any deviceNathan Binkert
2005-11-02Merge zizzer:/bk/m5Ali Saidi
2005-11-02Add Mem/Ethernet latency variability parameterAli Saidi
2005-10-21Major changes to sinic device model. Rearrage read/write, betterNathan Binkert
2005-10-18Shuffle around device names to make things easier to read.Nathan Binkert
2005-10-18use the dedicated flag, no more exposing the m5reg directlyNathan Binkert
2005-10-06Add execution trace object to Root.Steve Reinhardt
2005-10-01Add executable parameter to LiveProcess. This allows the argv[0] value toSteve Reinhardt
2005-09-17Fix the EtherDump parametersNathan Binkert
2005-09-01Convert type of max_time and progress_interval parametersSteve Reinhardt
2005-08-15Changes for getting FreeBSD to run.Miguel Serrano
2005-06-29Allow CPUs to specify their own CPU ids.Nathan Binkert
2005-06-27Implement a state machine clock that acutally limits how fastNathan Binkert
2005-06-22Move max_time and progress_interval parameters to the RootNathan Binkert
2005-06-09BaseSystem was renamed to SystemNathan Binkert
2005-06-05make all of the turbolaser stuff only compile if ALPHA_TLASERNathan Binkert
2005-06-05split uart into urt8250 and uart8530Ali Saidi
2005-06-04BaseSystem -> SystemNathan Binkert
2005-06-02Fix-up some config issuesNathan Binkert
2005-06-01Standardize clock parameter names to 'clock'.Steve Reinhardt
2005-05-29Major cleanup of python config code.Steve Reinhardt
2005-05-17Merge ktlim@zizzer:/bk/m5 into zamp.eecs.umich.edu:/z/ktlim2/current/m5Kevin Lim
2005-05-13Add mem_trace parameter to BaseCache.Steve Reinhardt
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