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| author | Giacomo Gabrielli <giacomo.gabrielli@arm.com> | 2018-10-16 16:04:08 +0100 |
|---|---|---|
| committer | Giacomo Gabrielli <giacomo.gabrielli@arm.com> | 2019-01-30 16:57:54 +0000 |
| commit | 25474167e5b247d1b91fbf802c5b396a63ae705e (patch) | |
| tree | b509597b23d792734f55c33b8125eebfbd9cd3a5 /src/arch/SConscript | |
| parent | c6f5db8743f19b02a38146d9cf2a829883387008 (diff) | |
| download | gem5-25474167e5b247d1b91fbf802c5b396a63ae705e.tar.xz | |
arch,cpu: Add vector predicate registers
Latest-gen. vector/SIMD extensions, including the Arm Scalable Vector
Extension (SVE), introduce the notion of a predicate register file.
This changeset adds this feature across architectures and CPU models.
Change-Id: Iebcadbad89c0a582ff8b1b70de353305db603946
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13715
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/arch/SConscript')
| -rw-r--r-- | src/arch/SConscript | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/arch/SConscript b/src/arch/SConscript index 5ea7a6a75..ed583aa5a 100644 --- a/src/arch/SConscript +++ b/src/arch/SConscript @@ -1,6 +1,6 @@ # -*- mode:python -*- -# Copyright (c) 2016 ARM Limited +# Copyright (c) 2016-2017 ARM Limited # All rights reserved. # # The license below extends only to copyright in the software and shall @@ -226,6 +226,8 @@ Export('ISADesc') DebugFlag('IntRegs') DebugFlag('FloatRegs') DebugFlag('VecRegs') +DebugFlag('VecPredRegs') DebugFlag('CCRegs') DebugFlag('MiscRegs') -CompoundFlag('Registers', [ 'IntRegs', 'FloatRegs', 'CCRegs', 'MiscRegs' ]) +CompoundFlag('Registers', [ 'IntRegs', 'FloatRegs', 'VecRegs', 'VecPredRegs', + 'CCRegs', 'MiscRegs' ]) |