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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2014-01-24 15:29:30 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2014-01-24 15:29:30 -0600 |
| commit | 7d0344704a9ecc566d82ad43ec44b4becbaf4d77 (patch) | |
| tree | 4281e9fe0ff9480698ed697027e411da73e78d47 /src/arch/alpha/AlphaISA.py | |
| parent | 3436de0c2ad467c65066e48969a7c12bdbbb3d26 (diff) | |
| download | gem5-7d0344704a9ecc566d82ad43ec44b4becbaf4d77.tar.xz | |
arch, cpu: Add support for flattening misc register indexes.
With ARMv8 support the same misc register id results in accessing different
registers depending on the current mode of the processor. This patch adds
the same orthogonality to the misc register file as the others (int, float, cc).
For all the othre ISAs this is currently a null-implementation.
Additionally, a system variable is added to all the ISA objects.
Diffstat (limited to 'src/arch/alpha/AlphaISA.py')
| -rw-r--r-- | src/arch/alpha/AlphaISA.py | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/arch/alpha/AlphaISA.py b/src/arch/alpha/AlphaISA.py index 64c9e4733..d85354704 100644 --- a/src/arch/alpha/AlphaISA.py +++ b/src/arch/alpha/AlphaISA.py @@ -35,9 +35,13 @@ # # Authors: Andreas Sandberg +from m5.params import * +from m5.proxy import * from m5.SimObject import SimObject class AlphaISA(SimObject): type = 'AlphaISA' cxx_class = 'AlphaISA::ISA' cxx_header = "arch/alpha/isa.hh" + + system = Param.System(Parent.any, "System this ISA object belongs to") |