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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:20 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:20 -0700 |
| commit | 32daf6fc3fd34af0023ae74c2a1f8dd597f87242 (patch) | |
| tree | 0868fb00a7546d90971bc18acd4f7b0bbce558c0 /src/arch/alpha/isa | |
| parent | 3e2cad8370d99f45ecf4d922d3ac8213e0d72644 (diff) | |
| download | gem5-32daf6fc3fd34af0023ae74c2a1f8dd597f87242.tar.xz | |
Registers: Add an ISA object which replaces the MiscRegFile.
This object encapsulates (or will eventually) the identity and characteristics
of the ISA in the CPU.
Diffstat (limited to 'src/arch/alpha/isa')
| -rw-r--r-- | src/arch/alpha/isa/main.isa | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa index aea44976c..d2b37590a 100644 --- a/src/arch/alpha/isa/main.isa +++ b/src/arch/alpha/isa/main.isa @@ -55,6 +55,7 @@ output header {{ output decoder {{ #include <cmath> +#include "arch/alpha/miscregfile.hh" #include "base/cprintf.hh" #include "base/fenv.hh" #include "base/loader/symtab.hh" @@ -71,6 +72,7 @@ output exec {{ #include "base/cp_annotate.hh" #include "sim/pseudo_inst.hh" #include "arch/alpha/ipr.hh" +#include "arch/alpha/miscregfile.hh" #include "base/fenv.hh" #include "config/ss_compatible_fp.hh" #include "cpu/base.hh" |