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| author | Mitch Hayenga <mitch.hayenga@arm.com> | 2015-09-30 11:14:19 -0500 |
|---|---|---|
| committer | Mitch Hayenga <mitch.hayenga@arm.com> | 2015-09-30 11:14:19 -0500 |
| commit | a5c4eb3de9deb3a71a6a5230a25ff5962e584980 (patch) | |
| tree | 874b659c6a5eaa1316cde9eb82ec7d08badf638a /src/arch/alpha/isa | |
| parent | e255fa053f8d105de8d188077a318124a3aad9ce (diff) | |
| download | gem5-a5c4eb3de9deb3a71a6a5230a25ff5962e584980.tar.xz | |
isa,cpu: Add support for FS SMT Interrupts
Adds per-thread interrupt controllers and thread/context logic
so that interrupts properly get routed in SMT systems.
Diffstat (limited to 'src/arch/alpha/isa')
| -rw-r--r-- | src/arch/alpha/isa/decoder.isa | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa index c77ca434f..e61bb43ff 100644 --- a/src/arch/alpha/isa/decoder.isa +++ b/src/arch/alpha/isa/decoder.isa @@ -943,7 +943,7 @@ decode OPCODE default Unknown::unknown() { 0x01: quiesce({{ // Don't sleep if (unmasked) interrupts are pending Interrupts* interrupts = - xc->tcBase()->getCpuPtr()->getInterruptController(); + xc->tcBase()->getCpuPtr()->getInterruptController(0); if (interrupts->checkInterrupts(xc->tcBase())) { PseudoInst::quiesceSkip(xc->tcBase()); } else { |