Merge ktlim@zizzer:/bk/newmem

into  zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem

--HG--
extra : convert_revision : 0c2db1e1b5fdb91c1ac5705ab872a6bfb575a67a

3 files changed, 27 insertions, 24 deletions

diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index 5bd19b677..7014d4c22 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -629,7 +629,7 @@ decode OPCODE default Unknown::unknown() {
         /* Rb is a fake dependency so here is a fun way to get
          * the parser to understand that.
          */
-                Ra = xc->readMiscRegWithEffect(AlphaISA::IPR_CC, fault) + (Rb & 0);
+                Ra = xc->readMiscRegWithEffect(AlphaISA::IPR_CC) + (Rb & 0);
 
 #else
                 Ra = curTick;
@@ -661,12 +661,12 @@ decode OPCODE default Unknown::unknown() {
 #if FULL_SYSTEM
         format BasicOperate {
             0xe000: rc({{
-                Ra = xc->readIntrFlag();
-                xc->setIntrFlag(0);
+                Ra = IntrFlag;
+                IntrFlag = 0;
             }}, IsNonSpeculative, IsUnverifiable);
             0xf000: rs({{
-                Ra = xc->readIntrFlag();
-                xc->setIntrFlag(1);
+                Ra = IntrFlag;
+                IntrFlag = 1;
             }}, IsNonSpeculative, IsUnverifiable);
         }
 #else
@@ -681,7 +681,7 @@ decode OPCODE default Unknown::unknown() {
     0x00: CallPal::call_pal({{
         if (!palValid ||
             (palPriv
-             && xc->readMiscRegWithEffect(AlphaISA::IPR_ICM, fault) != AlphaISA::mode_kernel)) {
+             && xc->readMiscRegWithEffect(AlphaISA::IPR_ICM) != AlphaISA::mode_kernel)) {
             // invalid pal function code, or attempt to do privileged
             // PAL call in non-kernel mode
             fault = new UnimplementedOpcodeFault;
@@ -693,7 +693,7 @@ decode OPCODE default Unknown::unknown() {
 
             if (dopal) {
                 xc->setMiscRegWithEffect(AlphaISA::IPR_EXC_ADDR, NPC);
-                NPC = xc->readMiscRegWithEffect(AlphaISA::IPR_PAL_BASE, fault) + palOffset;
+                NPC = xc->readMiscRegWithEffect(AlphaISA::IPR_PAL_BASE) + palOffset;
             }
         }
     }}, IsNonSpeculative);
@@ -745,7 +745,13 @@ decode OPCODE default Unknown::unknown() {
         0: OpcdecFault::hw_mfpr();
         format HwMoveIPR {
             1: hw_mfpr({{
-                Ra = xc->readMiscRegWithEffect(ipr_index, fault);
+                int miscRegIndex = (ipr_index < MaxInternalProcRegs) ?
+                        IprToMiscRegIndex[ipr_index] : -1;
+                if(miscRegIndex < 0 || !IprIsReadable(miscRegIndex) ||
+                    miscRegIndex >= NumInternalProcRegs)
+                        fault = new UnimplementedOpcodeFault;
+                else
+                    Ra = xc->readMiscRegWithEffect(miscRegIndex);
             }}, IsIprAccess);
         }
     }
@@ -754,7 +760,13 @@ decode OPCODE default Unknown::unknown() {
         0: OpcdecFault::hw_mtpr();
         format HwMoveIPR {
             1: hw_mtpr({{
-                xc->setMiscRegWithEffect(ipr_index, Ra);
+                int miscRegIndex = (ipr_index < MaxInternalProcRegs) ?
+                        IprToMiscRegIndex[ipr_index] : -1;
+                if(miscRegIndex < 0 || !IprIsWritable(miscRegIndex) ||
+                    miscRegIndex >= NumInternalProcRegs)
+                        fault = new UnimplementedOpcodeFault;
+                else
+                    xc->setMiscRegWithEffect(miscRegIndex, Ra);
                 if (traceData) { traceData->setData(Ra); }
             }}, IsIprAccess);
         }
@@ -783,12 +795,6 @@ decode OPCODE default Unknown::unknown() {
             0x04: quiesceTime({{
                 R0 = AlphaPseudo::quiesceTime(xc->tcBase());
             }}, IsNonSpeculative, IsUnverifiable);
-            0x10: ivlb({{
-                AlphaPseudo::ivlb(xc->tcBase());
-            }}, No_OpClass, IsNonSpeculative);
-            0x11: ivle({{
-                AlphaPseudo::ivle(xc->tcBase());
-            }}, No_OpClass, IsNonSpeculative);
             0x20: m5exit_old({{
                 AlphaPseudo::m5exit_old(xc->tcBase());
             }}, No_OpClass, IsNonSpeculative);
diff --git a/src/arch/alpha/isa/fp.isa b/src/arch/alpha/isa/fp.isa
index b4339a1b7..3b5575f62 100644
--- a/src/arch/alpha/isa/fp.isa
+++ b/src/arch/alpha/isa/fp.isa
@@ -46,7 +46,7 @@ output exec {{
     inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
     {
         Fault fault = NoFault;	// dummy... this ipr access should not fault
-        if (!EV5::ICSR_FPE(xc->readMiscRegWithEffect(AlphaISA::IPR_ICSR, fault))) {
+        if (!EV5::ICSR_FPE(xc->readMiscRegWithEffect(AlphaISA::IPR_ICSR))) {
             fault = new FloatEnableFault;
         }
         return fault;
@@ -229,7 +229,7 @@ def template FloatingPointExecute {{
             %(code)s;
         } else {
             fesetround(getC99RoundingMode(
-                           xc->readMiscReg(AlphaISA::Fpcr_DepTag)));
+                           xc->readMiscReg(AlphaISA::MISCREG_FPCR)));
             %(code)s;
             fesetround(FE_TONEAREST);
         }
diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa
index 2024b1117..6e65cf9d3 100644
--- a/src/arch/alpha/isa/main.isa
+++ b/src/arch/alpha/isa/main.isa
@@ -71,6 +71,7 @@ output exec {{
 #if FULL_SYSTEM
 #include "sim/pseudo_inst.hh"
 #endif
+#include "arch/alpha/ipr.hh"
 #include "base/fenv.hh"
 #include "config/ss_compatible_fp.hh"
 #include "cpu/base.hh"
@@ -183,8 +184,9 @@ def operands {{
     'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
     'Mem': ('Mem', 'uq', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
     'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4),
-    'Runiq': ('ControlReg', 'uq', 'TheISA::Uniq_DepTag', None, 1),
-    'FPCR':  (' ControlReg', 'uq', 'TheISA::Fpcr_DepTag', None, 1),
+    'Runiq': ('ControlReg', 'uq', 'MISCREG_UNIQ', None, 1),
+    'FPCR':  ('ControlReg', 'uq', 'MISCREG_FPCR', None, 1),
+    'IntrFlag': ('ControlReg', 'uq', 'MISCREG_INTR', None, 1),
     # The next two are hacks for non-full-system call-pal emulation
     'R0':  ('IntReg', 'uq', '0', None, 1),
     'R16': ('IntReg', 'uq', '16', None, 1),
@@ -214,11 +216,6 @@ output header {{
         /// live here and not in the AlphaISA namespace.
         enum DependenceTags {
             FP_Base_DepTag = AlphaISA::FP_Base_DepTag,
-            Fpcr_DepTag = AlphaISA::Fpcr_DepTag,
-            Uniq_DepTag = AlphaISA::Uniq_DepTag,
-            Lock_Flag_DepTag = AlphaISA::Lock_Flag_DepTag,
-            Lock_Addr_DepTag = AlphaISA::Lock_Addr_DepTag,
-            IPR_Base_DepTag = AlphaISA::IPR_Base_DepTag
         };
 
         /// Constructor.