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| author | Giacomo Gabrielli <Giacomo.Gabrielli@arm.com> | 2010-12-07 16:19:57 -0800 |
|---|---|---|
| committer | Giacomo Gabrielli <Giacomo.Gabrielli@arm.com> | 2010-12-07 16:19:57 -0800 |
| commit | 719f9a6d4fba16af38dcfd62b25a4d708156699f (patch) | |
| tree | 1a380efa6ed27b505fdf402e2a069d217c9a4eac /src/arch/alpha/locked_mem.hh | |
| parent | 4bbdd6ceb2639fe21408ab211b7c4c7e53adb249 (diff) | |
| download | gem5-719f9a6d4fba16af38dcfd62b25a4d708156699f.tar.xz | |
O3: Make all instructions that write a misc. register not perform the write until commit.
ARM instructions updating cumulative flags (ARM FP exceptions and saturation
flags) are not serialized.
Added aliases for ARM FP exceptions and saturation flags in FPSCR. Removed
write accesses to the FP condition codes for most ARM VFP instructions: only
VCMP and VCMPE instructions update the FP condition codes. Removed a potential
cause of seg. faults in the O3 model for NEON memory macro-ops (ARM).
Diffstat (limited to 'src/arch/alpha/locked_mem.hh')
| -rw-r--r-- | src/arch/alpha/locked_mem.hh | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/arch/alpha/locked_mem.hh b/src/arch/alpha/locked_mem.hh index 86958e4c5..24d028b54 100644 --- a/src/arch/alpha/locked_mem.hh +++ b/src/arch/alpha/locked_mem.hh @@ -55,8 +55,8 @@ template <class XC> inline void handleLockedRead(XC *xc, Request *req) { - xc->setMiscRegNoEffect(MISCREG_LOCKADDR, req->getPaddr() & ~0xf); - xc->setMiscRegNoEffect(MISCREG_LOCKFLAG, true); + xc->setMiscReg(MISCREG_LOCKADDR, req->getPaddr() & ~0xf); + xc->setMiscReg(MISCREG_LOCKFLAG, true); } @@ -70,13 +70,13 @@ handleLockedWrite(XC *xc, Request *req) req->setExtraData(2); } else { // standard store conditional - bool lock_flag = xc->readMiscRegNoEffect(MISCREG_LOCKFLAG); - Addr lock_addr = xc->readMiscRegNoEffect(MISCREG_LOCKADDR); + bool lock_flag = xc->readMiscReg(MISCREG_LOCKFLAG); + Addr lock_addr = xc->readMiscReg(MISCREG_LOCKADDR); if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) { // Lock flag not set or addr mismatch in CPU; // don't even bother sending to memory system req->setExtraData(0); - xc->setMiscRegNoEffect(MISCREG_LOCKFLAG, false); + xc->setMiscReg(MISCREG_LOCKFLAG, false); // the rest of this code is not architectural; // it's just a debugging aid to help detect // livelock by warning on long sequences of failed |