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| author | Min Kyu Jeong <minkyu.jeong@arm.com> | 2010-08-25 19:10:43 -0500 |
|---|---|---|
| committer | Min Kyu Jeong <minkyu.jeong@arm.com> | 2010-08-25 19:10:43 -0500 |
| commit | e1168e72ca8ae370a1989220a202347980c6a4d2 (patch) | |
| tree | 2d8b3766e7ad5261d13aa7d1a0becbf6aee2f7eb /src/arch/alpha/registers.hh | |
| parent | edca5f7da6bad677dfc1ea69fff904554181cc17 (diff) | |
| download | gem5-e1168e72ca8ae370a1989220a202347980c6a4d2.tar.xz | |
ARM: Fixed register flattening logic (FP_Base_DepTag was set too low)
When decoding a srs instruction, invalid mode encoding returns invalid instruction.
This can happen when garbage instructions are fetched from mispredicted path
Diffstat (limited to 'src/arch/alpha/registers.hh')
| -rw-r--r-- | src/arch/alpha/registers.hh | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/arch/alpha/registers.hh b/src/arch/alpha/registers.hh index ec36ff751..d8752d520 100644 --- a/src/arch/alpha/registers.hh +++ b/src/arch/alpha/registers.hh @@ -101,7 +101,8 @@ enum DependenceTags { // 0..31 are the integer regs 0..31 // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag) FP_Base_DepTag = 40, - Ctrl_Base_DepTag = 72 + Ctrl_Base_DepTag = 72, + Max_DepTag = Ctrl_Base_DepTag + NumMiscRegs + NumInternalProcRegs }; } // namespace AlphaISA |