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| author | Korey Sewell <ksewell@umich.edu> | 2011-06-19 21:43:41 -0400 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2011-06-19 21:43:41 -0400 |
| commit | 5ef0b7a9db3c6ec4ca191c2e9381719e1e694873 (patch) | |
| tree | 718fdaf81b288b91bbac7eb2a8bae285d2dc39ac /src/arch/alpha/tlb.cc | |
| parent | 716e447da8424386f2c3448c17891927aeb49f67 (diff) | |
| download | gem5-5ef0b7a9db3c6ec4ca191c2e9381719e1e694873.tar.xz | |
inorder/dtb: make sure DTB translate correct address
The DTB expects the correct PC in the ThreadContext
but how if the memory accesses are speculative? Shouldn't
we send along the requestor's PC to the translate functions?
Diffstat (limited to 'src/arch/alpha/tlb.cc')
| -rw-r--r-- | src/arch/alpha/tlb.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc index 2c7e6732a..fbe188973 100644 --- a/src/arch/alpha/tlb.cc +++ b/src/arch/alpha/tlb.cc @@ -457,7 +457,7 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write) return new DtbAlignmentFault(req->getVaddr(), req->getFlags(), flags); } - if (PcPAL(tc->pcState().pc())) { + if (PcPAL(req->getPC())) { mode = (req->getFlags() & Request::ALTMODE) ? (mode_type)ALT_MODE_AM( tc->readMiscRegNoEffect(IPR_ALT_MODE)) |