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authorGabe Black <gblack@eecs.umich.edu>2006-08-11 20:21:35 -0400
committerGabe Black <gblack@eecs.umich.edu>2006-08-11 20:21:35 -0400
commitec26f0bb3d3d0af9dc87e5e3f25c2b90f2db0332 (patch)
treef4f1307f30e0941f448087992db77562d9f7330c /src/arch/alpha
parent800e6ecc07d01c49808cc4f9597d94cc8cfd9fae (diff)
downloadgem5-ec26f0bb3d3d0af9dc87e5e3f25c2b90f2db0332.tar.xz
Started adding a system to output data after every instruction.
src/arch/alpha/regfile.hh: src/arch/mips/regfile/float_regfile.hh: src/arch/mips/regfile/int_regfile.hh: src/arch/mips/regfile/misc_regfile.hh: src/cpu/exetrace.hh: Added functions to start to support dumping register values once per cycle. src/cpu/exetrace.cc: Added some code to support printing the value of registers after each cycle. src/python/m5/main.py: Options to turn on output after every instruction. They are commented out. --HG-- extra : convert_revision : 168a48a6b98ab6be412a96bdee831c71906958b0
Diffstat (limited to 'src/arch/alpha')
-rw-r--r--src/arch/alpha/regfile.hh15
1 files changed, 15 insertions, 0 deletions
diff --git a/src/arch/alpha/regfile.hh b/src/arch/alpha/regfile.hh
index c31619408..43b48a0ab 100644
--- a/src/arch/alpha/regfile.hh
+++ b/src/arch/alpha/regfile.hh
@@ -45,6 +45,21 @@ class ThreadContext;
namespace AlphaISA
{
+ static inline std::string getIntRegName(RegIndex)
+ {
+ return "";
+ }
+
+ static inline std::string getFloatRegName(RegIndex)
+ {
+ return "";
+ }
+
+ static inline std::string getMiscRegName(RegIndex)
+ {
+ return "";
+ }
+
class IntRegFile
{
protected: