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| author | Gabe Black <gblack@eecs.umich.edu> | 2012-05-26 13:44:46 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2012-05-26 13:44:46 -0700 |
| commit | 0cba96ba6a5d7a4dab2a63b14149c49dfbfbb3bc (patch) | |
| tree | 1e4e1372b76ed021060d560c2ee1a474f4b22ef0 /src/arch/arm/SConscript | |
| parent | eae1e97fb002b44a9d8c46df2da1ddc1d0156ce4 (diff) | |
| download | gem5-0cba96ba6a5d7a4dab2a63b14149c49dfbfbb3bc.tar.xz | |
CPU: Merge the predecoder and decoder.
These classes are always used together, and merging them will give the ISAs
more flexibility in how they cache things and manage the process.
--HG--
rename : src/arch/x86/predecoder_tables.cc => src/arch/x86/decoder_tables.cc
Diffstat (limited to 'src/arch/arm/SConscript')
| -rw-r--r-- | src/arch/arm/SConscript | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript index 0f94455bd..44b6286a0 100644 --- a/src/arch/arm/SConscript +++ b/src/arch/arm/SConscript @@ -62,7 +62,6 @@ if env['TARGET_ISA'] == 'arm': Source('linux/system.cc') Source('miscregs.cc') Source('nativetrace.cc') - Source('predecoder.cc') Source('process.cc') Source('remote_gdb.cc') Source('stacktrace.cc') @@ -78,9 +77,9 @@ if env['TARGET_ISA'] == 'arm': SimObject('ArmTLB.py') DebugFlag('Arm') - DebugFlag('TLBVerbose') + DebugFlag('Decoder', "Instructions returned by the predecoder") DebugFlag('Faults', "Trace Exceptions, interrupts, svc/swi") - DebugFlag('Predecoder', "Instructions returned by the predecoder") + DebugFlag('TLBVerbose') # Add in files generated by the ISA description. isa_desc_files = env.ISADesc('isa/main.isa') |