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| author | Ciro Santilli <ciro.santilli@arm.com> | 2018-12-21 14:25:24 +0000 |
|---|---|---|
| committer | Ciro Santilli <ciro.santilli@arm.com> | 2019-01-22 11:35:12 +0000 |
| commit | 0f024be0ca5bd9830f8fd84456894c965cc7c16c (patch) | |
| tree | 77f5e94fcee6967dc64adaa4db99cc6bfb2bf0ac /src/arch/arm/SConscript | |
| parent | 6064582d714b40766e23f41a788f013fb435fdec (diff) | |
| download | gem5-0f024be0ca5bd9830f8fd84456894c965cc7c16c.tar.xz | |
arch-arm: implement the GDB XML target description for ARM
The supported registers are essentially the same as before this patch,
but it is now trivial to make new registers visible in future commits.
Change-Id: Id15b7aeccca824c342e49a626d2877179474f3d4
Reviewed-on: https://gem5-review.googlesource.com/c/15138
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/SConscript')
| -rw-r--r-- | src/arch/arm/SConscript | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript index c84c69ba6..a1063f039 100644 --- a/src/arch/arm/SConscript +++ b/src/arch/arm/SConscript @@ -105,3 +105,10 @@ if env['TARGET_ISA'] == 'arm': # Add files generated by the ISA description. ISADesc('isa/main.isa', decoder_splits=3, exec_splits=6) + + GdbXml('arm/arm-with-neon.xml', 'gdb_xml_arm_target') + GdbXml('arm/arm-core.xml', 'gdb_xml_arm_core') + GdbXml('arm/arm-vfpv3.xml', 'gdb_xml_arm_vfpv3') + GdbXml('aarch64.xml', 'gdb_xml_aarch64_target') + GdbXml('aarch64-core.xml', 'gdb_xml_aarch64_core') + GdbXml('aarch64-fpu.xml', 'gdb_xml_aarch64_fpu') |