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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-05-13 17:27:01 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-05-13 17:27:01 -0500 |
| commit | 2178859b76bb13b1d225fc4dffa04d43d2db2e14 (patch) | |
| tree | c57a005891e10565c9e7552cb90037a667001807 /src/arch/arm/faults.cc | |
| parent | 4bf48a11efd7253bdb7a61da42d2bc754033757b (diff) | |
| download | gem5-2178859b76bb13b1d225fc4dffa04d43d2db2e14.tar.xz | |
ARM: Break up condition codes into normal flags, saturation, and simd.
This change splits out the condcodes from being one monolithic register
into three blocks that are updated independently. This allows CPUs
to not have to do RMW operations on the flags registers for instructions
that don't write all flags.
Diffstat (limited to 'src/arch/arm/faults.cc')
| -rw-r--r-- | src/arch/arm/faults.cc | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc index 03a65ea88..4b58a7144 100644 --- a/src/arch/arm/faults.cc +++ b/src/arch/arm/faults.cc @@ -107,7 +107,9 @@ ArmFault::invoke(ThreadContext *tc, StaticInstPtr inst) SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR) | - tc->readIntReg(INTREG_CONDCODES); + tc->readIntReg(INTREG_CONDCODES_F) | + tc->readIntReg(INTREG_CONDCODES_Q) | + tc->readIntReg(INTREG_CONDCODES_GE); Addr curPc M5_VAR_USED = tc->pcState().pc(); ITSTATE it = tc->pcState().itstate(); saved_cpsr.it2 = it.top6; |