diff options
author | Nathanael Premillieu <nathanael.premillieu@arm.com> | 2017-04-05 12:46:06 -0500 |
---|---|---|
committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2017-07-05 14:43:49 +0000 |
commit | 5e8287d2e2eaf058495442ea9e32fafc343a0b53 (patch) | |
tree | 7d0891b8984926f8e404d6ca8247f45695f9fc9b /src/arch/arm/insts/branch64.cc | |
parent | 864f87f9c56a66dceeca0f4e9470fbaa3001b627 (diff) | |
download | gem5-5e8287d2e2eaf058495442ea9e32fafc343a0b53.tar.xz |
arch, cpu: Architectural Register structural indexing
Replace the unified register mapping with a structure associating
a class and an index. It is now much easier to know which class of
register the index is referring to. Also, when adding a new class
there is no need to modify existing ones.
Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2700
Diffstat (limited to 'src/arch/arm/insts/branch64.cc')
-rw-r--r-- | src/arch/arm/insts/branch64.cc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/arch/arm/insts/branch64.cc b/src/arch/arm/insts/branch64.cc index 49ba3402a..d0a4f2924 100644 --- a/src/arch/arm/insts/branch64.cc +++ b/src/arch/arm/insts/branch64.cc @@ -95,7 +95,7 @@ BranchReg64::generateDisassembly( { std::stringstream ss; printMnemonic(ss, "", false); - printReg(ss, op1); + printIntReg(ss, op1); return ss.str(); } @@ -106,7 +106,7 @@ BranchRet64::generateDisassembly( std::stringstream ss; printMnemonic(ss, "", false); if (op1 != INTREG_X30) - printReg(ss, op1); + printIntReg(ss, op1); return ss.str(); } @@ -125,7 +125,7 @@ BranchImmReg64::generateDisassembly( { std::stringstream ss; printMnemonic(ss, "", false); - printReg(ss, op1); + printIntReg(ss, op1); ccprintf(ss, ", "); printTarget(ss, pc + imm, symtab); return ss.str(); @@ -137,7 +137,7 @@ BranchImmImmReg64::generateDisassembly( { std::stringstream ss; printMnemonic(ss, "", false); - printReg(ss, op1); + printIntReg(ss, op1); ccprintf(ss, ", #%#x, ", imm1); printTarget(ss, pc + imm2, symtab); return ss.str(); |