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| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-10-01 08:05:51 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-10-01 08:05:51 -0400 |
| commit | 10f82934be924f265af4f10b15ca66106171f770 (patch) | |
| tree | e8e92c73422751d4ee26c3b87ceae204fa520751 /src/arch/arm/insts/misc.hh | |
| parent | ff2d58f935c434e89a499474d3bda76f476e6d25 (diff) | |
| download | gem5-10f82934be924f265af4f10b15ca66106171f770.tar.xz | |
arm: More UBSan cleanups after additional full-system runs
Some incorrect casting to IntRegIndex, and a few uninitialized members
in the i8254xGBe device.
Diffstat (limited to 'src/arch/arm/insts/misc.hh')
| -rw-r--r-- | src/arch/arm/insts/misc.hh | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/arch/arm/insts/misc.hh b/src/arch/arm/insts/misc.hh index 4217dc6f1..0c864559e 100644 --- a/src/arch/arm/insts/misc.hh +++ b/src/arch/arm/insts/misc.hh @@ -97,13 +97,13 @@ class MsrRegOp : public MsrBase class MrrcOp : public PredOp { protected: - IntRegIndex op1; + MiscRegIndex op1; IntRegIndex dest; IntRegIndex dest2; uint32_t imm; MrrcOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, - IntRegIndex _op1, IntRegIndex _dest, IntRegIndex _dest2, + MiscRegIndex _op1, IntRegIndex _dest, IntRegIndex _dest2, uint32_t _imm) : PredOp(mnem, _machInst, __opClass), op1(_op1), dest(_dest), dest2(_dest2), imm(_imm) @@ -117,11 +117,11 @@ class McrrOp : public PredOp protected: IntRegIndex op1; IntRegIndex op2; - IntRegIndex dest; + MiscRegIndex dest; uint32_t imm; McrrOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, - IntRegIndex _op1, IntRegIndex _op2, IntRegIndex _dest, + IntRegIndex _op1, IntRegIndex _op2, MiscRegIndex _dest, uint32_t _imm) : PredOp(mnem, _machInst, __opClass), op1(_op1), op2(_op2), dest(_dest), imm(_imm) |