gem5 - gem5

Age	Commit message (Expand)	Author
2019-01-22	arch-arm: Move AArch32 IMPLEMENTATION DEFINED registers	Giacomo Travaglini
2018-03-26	arch: Fix all override related warnings.	Gabe Black
2018-02-07	arch-arm: Fix printing of the data cache maintenance instructions	Nikos Nikoleris
2017-12-05	arm: Add support for the mcr dc{ic,i,c}mvac, dccmvau instructions	Nikos Nikoleris
2014-11-14	arm: Fixes based on UBSan and static analysis	Andreas Hansson
2014-10-01	arm: More UBSan cleanups after additional full-system runs	Andreas Hansson
2014-09-27	arm: Fixed undefined behaviours identified by gcc	Andreas Hansson
2014-01-24	arm: Add support for ARMv8 (AArch64 & AArch32)	ARM gem5 Developers
2010-06-02	ARM: Make undefined instructions obey predication.	Gabe Black
2010-06-02	ARM: Add a new RegImmOp base class.	Gabe Black
2010-06-02	ARM: Add a RegRegImmOp base class.	Gabe Black
2010-06-02	ARM: Widen the immediate fields in the misc instruction classes.	Gabe Black
2010-06-02	ARM: Make a base class for instructions that use only an immediate.	Gabe Black
2010-06-02	ARM: Rename the RevOp base class to something more generic.	Gabe Black
2010-06-02	ARM: Add a register, immediate, immediate to register base for [su]bfx.	Gabe Black
2010-06-02	ARM: Add a base class to support usada8.	Gabe Black
2010-06-02	ARM: Add a base class for the sel instruction.	Gabe Black
2010-06-02	ARM: Add a base class for extend and add instructions.	Gabe Black
2010-06-02	ARM: Generalize the saturation instruction bases for use in other instructions.	Gabe Black
2010-06-02	ARM: Implement base classes for the saturation instructions.	Gabe Black
2010-06-02	ARM: Add base classes suitable for the REV* instructions.	Gabe Black
2010-06-02	ARM: Define versions of MSR and MRS outside the decoder.	Gabe Black