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author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-10-25 11:14:47 +0100 |
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committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-01-22 09:17:22 +0000 |
commit | 12eac0c88e21ddc76593079127a4507558cddc40 (patch) | |
tree | 00cd013d61e15795421a8ea9d5cafe6c6c62ba33 /src/arch/arm/insts/misc.hh | |
parent | a0649ee1e90e6c71f74425457c381e8b6c5d0d43 (diff) | |
download | gem5-12eac0c88e21ddc76593079127a4507558cddc40.tar.xz |
arch-arm: Move AArch32 IMPLEMENTATION DEFINED registers
Moving AArch32 instruction accessing IMPLEMENTATION DEFINED registers
from pseudo.[cc/hh] to misc.[cc/hh] in order to symmetrically match
with AArch64 implementation.
Change-Id: I27b0d65925d7965589b765269ae54129426e4c88
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15735
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/insts/misc.hh')
-rw-r--r-- | src/arch/arm/insts/misc.hh | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/src/arch/arm/insts/misc.hh b/src/arch/arm/insts/misc.hh index a036b2e11..e1f27433d 100644 --- a/src/arch/arm/insts/misc.hh +++ b/src/arch/arm/insts/misc.hh @@ -374,4 +374,46 @@ class UnknownOp : public PredOp Addr pc, const SymbolTable *symtab) const override; }; +/** + * Certain mrc/mcr instructions act as nops or flush the pipe based on what + * register the instruction is trying to access. This inst/class exists so that + * we can still check for hyp traps, as the normal nop instruction + * does not. + */ +class McrMrcMiscInst : public ArmStaticInst +{ + protected: + uint64_t iss; + MiscRegIndex miscReg; + + public: + McrMrcMiscInst(const char *_mnemonic, ExtMachInst _machInst, + uint64_t _iss, MiscRegIndex _miscReg); + + Fault execute(ExecContext *xc, + Trace::InstRecord *traceData) const override; + + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; + +}; + +/** + * This class is also used for IMPLEMENTATION DEFINED registers, whose mcr/mrc + * behaviour is trappable even for unimplemented registers. + */ +class McrMrcImplDefined : public McrMrcMiscInst +{ + public: + McrMrcImplDefined(const char *_mnemonic, ExtMachInst _machInst, + uint64_t _iss, MiscRegIndex _miscReg); + + Fault execute(ExecContext *xc, + Trace::InstRecord *traceData) const override; + + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; + +}; + #endif |