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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:07 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:07 -0500 |
| commit | 498f9d925e0339389a19bb63d9508e6c780ba04b (patch) | |
| tree | 00a1726357e965be3a12208c6fcd59e646753bd6 /src/arch/arm/insts/misc.hh | |
| parent | f581fd3f899648f8699f53ecdc913e7d50c26f8f (diff) | |
| download | gem5-498f9d925e0339389a19bb63d9508e6c780ba04b.tar.xz | |
ARM: Add a base class for the sel instruction.
Diffstat (limited to 'src/arch/arm/insts/misc.hh')
| -rw-r--r-- | src/arch/arm/insts/misc.hh | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/src/arch/arm/insts/misc.hh b/src/arch/arm/insts/misc.hh index d990070fb..8ab0b352a 100644 --- a/src/arch/arm/insts/misc.hh +++ b/src/arch/arm/insts/misc.hh @@ -142,6 +142,22 @@ class RegRegRegImmOp : public PredOp std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; }; +class RegRegRegOp : public PredOp +{ + protected: + IntRegIndex dest; + IntRegIndex op1; + IntRegIndex op2; + + RegRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, + IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2) : + PredOp(mnem, _machInst, __opClass), + dest(_dest), op1(_op1), op2(_op2) + {} + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; +}; + class RegImmRegShiftOp : public PredOp { protected: |