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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:12 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:12 -0500 |
| commit | 6976b4890a307a2d8584b4e512e3f6d728e59ad5 (patch) | |
| tree | 7da45cfa95788995d576793b49a9d7eb1c4c948e /src/arch/arm/insts/misc.hh | |
| parent | 186cfe3ae30970b43c09cccab6f004ea7d720838 (diff) | |
| download | gem5-6976b4890a307a2d8584b4e512e3f6d728e59ad5.tar.xz | |
ARM: Add a RegRegImmOp base class.
Diffstat (limited to 'src/arch/arm/insts/misc.hh')
| -rw-r--r-- | src/arch/arm/insts/misc.hh | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/src/arch/arm/insts/misc.hh b/src/arch/arm/insts/misc.hh index 79cec5732..53281400e 100644 --- a/src/arch/arm/insts/misc.hh +++ b/src/arch/arm/insts/misc.hh @@ -189,6 +189,23 @@ class RegRegRegOp : public PredOp std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; }; +class RegRegImmOp : public PredOp +{ + protected: + IntRegIndex dest; + IntRegIndex op1; + uint64_t imm; + + RegRegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, + IntRegIndex _dest, IntRegIndex _op1, + uint64_t _imm) : + PredOp(mnem, _machInst, __opClass), + dest(_dest), op1(_op1), imm(_imm) + {} + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; +}; + class RegRegImmImmOp : public PredOp { protected: |