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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:07 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:07 -0500 |
| commit | c643b1c2749703b7823d665a7d89d0333f5c6e95 (patch) | |
| tree | cb9f0c6bbe54fae00f0803830bc9b2a04eea2bf3 /src/arch/arm/insts/misc.hh | |
| parent | 64ade8316ee563448d8c8f98a70cc4d9d0c66707 (diff) | |
| download | gem5-c643b1c2749703b7823d665a7d89d0333f5c6e95.tar.xz | |
ARM: Add a base class to support usada8.
Diffstat (limited to 'src/arch/arm/insts/misc.hh')
| -rw-r--r-- | src/arch/arm/insts/misc.hh | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/src/arch/arm/insts/misc.hh b/src/arch/arm/insts/misc.hh index 8ab0b352a..7ee2d95f9 100644 --- a/src/arch/arm/insts/misc.hh +++ b/src/arch/arm/insts/misc.hh @@ -142,6 +142,24 @@ class RegRegRegImmOp : public PredOp std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; }; +class RegRegRegRegOp : public PredOp +{ + protected: + IntRegIndex dest; + IntRegIndex op1; + IntRegIndex op2; + IntRegIndex op3; + + RegRegRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, + IntRegIndex _dest, IntRegIndex _op1, + IntRegIndex _op2, IntRegIndex _op3) : + PredOp(mnem, _machInst, __opClass), + dest(_dest), op1(_op1), op2(_op2), op3(_op3) + {} + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; +}; + class RegRegRegOp : public PredOp { protected: |