diff options
| author | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2017-02-07 11:35:10 +0000 |
|---|---|---|
| committer | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2017-12-05 11:47:01 +0000 |
| commit | eeb36e5b6e81c6b9ea6a0c3c97573e762e58ae05 (patch) | |
| tree | 9ea079dc4bc5b04cfc4b84a32c06225670be69dd /src/arch/arm/insts/misc.hh | |
| parent | b9edb351454c2601070fb9432f23fc3914eb33c1 (diff) | |
| download | gem5-eeb36e5b6e81c6b9ea6a0c3c97573e762e58ae05.tar.xz | |
arm: Add support for the mcr dc{ic,i,c}mvac, dccmvau instructions
This patch adds support for the ARMv7 cache maintenance
intructions:
* mcr dccmvac cleans a VA to the PoC
* mcr dcimvac invalidates a VA to the PoC
* mcr dccimvac cleans and invalidates a VA to the PoC
* mcr dccmvau cleans a VA to the PoU
Change-Id: I6511f203039ca145cc9128ddf61d09d6d7e40c10
Reviewed-by: Stephan Diestelhorst <stephan.diestelhorst@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5059
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/arch/arm/insts/misc.hh')
| -rw-r--r-- | src/arch/arm/insts/misc.hh | 19 |
1 files changed, 18 insertions, 1 deletions
diff --git a/src/arch/arm/insts/misc.hh b/src/arch/arm/insts/misc.hh index c2dcaa847..72d1694c9 100644 --- a/src/arch/arm/insts/misc.hh +++ b/src/arch/arm/insts/misc.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010, 2012-2013 ARM Limited + * Copyright (c) 2010, 2012-2013, 2017 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -344,6 +344,23 @@ class RegImmRegShiftOp : public PredOp std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; }; +class MiscRegRegImmMemOp : public PredOp +{ + protected: + MiscRegIndex dest; + IntRegIndex op1; + uint64_t imm; + + MiscRegRegImmMemOp(const char *mnem, ExtMachInst _machInst, + OpClass __opClass, MiscRegIndex _dest, IntRegIndex _op1, + uint64_t _imm) : + PredOp(mnem, _machInst, __opClass), + dest(_dest), op1(_op1), imm(_imm) + {} + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; +}; + class UnknownOp : public PredOp { protected: |