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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:19 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:19 -0700 |
| commit | 2fb8d481ab37db60a27126d151be23fad10adc50 (patch) | |
| tree | dbe8bc41f7d296455588565c07fb0ca1829c3fe8 /src/arch/arm/insts/pred_inst.cc | |
| parent | ddcf084f162374bab8f42ed5ab17c7cd4b67a559 (diff) | |
| download | gem5-2fb8d481ab37db60a27126d151be23fad10adc50.tar.xz | |
ARM: Tune up predicated instruction decoding.
Diffstat (limited to 'src/arch/arm/insts/pred_inst.cc')
| -rw-r--r-- | src/arch/arm/insts/pred_inst.cc | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/src/arch/arm/insts/pred_inst.cc b/src/arch/arm/insts/pred_inst.cc index 539cfc2d2..f98db1c8e 100644 --- a/src/arch/arm/insts/pred_inst.cc +++ b/src/arch/arm/insts/pred_inst.cc @@ -32,10 +32,18 @@ namespace ArmISA { std::string -PredOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +PredIntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const { std::stringstream ss; - printDataInst(ss); + printDataInst(ss, false); + return ss.str(); +} + +std::string +PredImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +{ + std::stringstream ss; + printDataInst(ss, true); return ss.str(); } |