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| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-11-14 03:53:51 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-11-14 03:53:51 -0500 |
| commit | 481eb6ae8018d0478c23fda7c5f9f3fa4db8de89 (patch) | |
| tree | e9b449bc6a2e7b15255c7a3c2d5984e0a99b452c /src/arch/arm/insts | |
| parent | 9ffe0e7ba67ee194db885b96a7ed3630aed03584 (diff) | |
| download | gem5-481eb6ae8018d0478c23fda7c5f9f3fa4db8de89.tar.xz | |
arm: Fixes based on UBSan and static analysis
Another churn to clean up undefined behaviour, mostly ARM, but some
parts also touching the generic part of the code base.
Most of the fixes are simply ensuring that proper intialisation. One
of the more subtle changes is the return type of the sign-extension,
which is changed to uint64_t. This is to avoid shifting negative
values (undefined behaviour) in the ISA code.
Diffstat (limited to 'src/arch/arm/insts')
| -rw-r--r-- | src/arch/arm/insts/macromem.cc | 9 | ||||
| -rw-r--r-- | src/arch/arm/insts/mem64.hh | 2 | ||||
| -rw-r--r-- | src/arch/arm/insts/misc.hh | 1 | ||||
| -rw-r--r-- | src/arch/arm/insts/pred_inst.hh | 2 |
4 files changed, 9 insertions, 5 deletions
diff --git a/src/arch/arm/insts/macromem.cc b/src/arch/arm/insts/macromem.cc index 1ea968328..3158026db 100644 --- a/src/arch/arm/insts/macromem.cc +++ b/src/arch/arm/insts/macromem.cc @@ -1281,7 +1281,10 @@ VldSingleOp64::VldSingleOp64(const char *mnem, ExtMachInst machInst, RegIndex rm, uint8_t eSize, uint8_t dataSize, uint8_t numStructElems, uint8_t index, bool wb, bool replicate) : - PredMacroOp(mnem, machInst, __opClass) + PredMacroOp(mnem, machInst, __opClass), + eSize(0), dataSize(0), numStructElems(0), index(0), + wb(false), replicate(false) + { RegIndex vx = NumFloatV8ArchRegs / 4; RegIndex rnsp = (RegIndex) makeSP((IntRegIndex) rn); @@ -1352,7 +1355,9 @@ VstSingleOp64::VstSingleOp64(const char *mnem, ExtMachInst machInst, RegIndex rm, uint8_t eSize, uint8_t dataSize, uint8_t numStructElems, uint8_t index, bool wb, bool replicate) : - PredMacroOp(mnem, machInst, __opClass) + PredMacroOp(mnem, machInst, __opClass), + eSize(0), dataSize(0), numStructElems(0), index(0), + wb(false), replicate(false) { RegIndex vx = NumFloatV8ArchRegs / 4; RegIndex rnsp = (RegIndex) makeSP((IntRegIndex) rn); diff --git a/src/arch/arm/insts/mem64.hh b/src/arch/arm/insts/mem64.hh index 21c1e1ea8..933d34576 100644 --- a/src/arch/arm/insts/mem64.hh +++ b/src/arch/arm/insts/mem64.hh @@ -101,7 +101,7 @@ class Memory64 : public MightBeMicro64 Memory64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _base) : MightBeMicro64(mnem, _machInst, __opClass), - dest(_dest), base(_base), uops(NULL) + dest(_dest), base(_base), uops(NULL), memAccessFlags(0) { baseIsSP = isSP(_base); } diff --git a/src/arch/arm/insts/misc.hh b/src/arch/arm/insts/misc.hh index 0c864559e..c2dcaa847 100644 --- a/src/arch/arm/insts/misc.hh +++ b/src/arch/arm/insts/misc.hh @@ -294,7 +294,6 @@ class RegImmImmOp : public PredOp { protected: IntRegIndex dest; - IntRegIndex op1; uint64_t imm1; uint64_t imm2; diff --git a/src/arch/arm/insts/pred_inst.hh b/src/arch/arm/insts/pred_inst.hh index 8a335879b..09ebbb120 100644 --- a/src/arch/arm/insts/pred_inst.hh +++ b/src/arch/arm/insts/pred_inst.hh @@ -312,7 +312,7 @@ class PredMacroOp : public PredOp /// Constructor PredMacroOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : PredOp(mnem, _machInst, __opClass), - numMicroops(0) + numMicroops(0), microOps(nullptr) { // We rely on the subclasses of this object to handle the // initialization of the micro-operations, since they are |