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authorGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:12 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:12 -0500
commit6976b4890a307a2d8584b4e512e3f6d728e59ad5 (patch)
tree7da45cfa95788995d576793b49a9d7eb1c4c948e /src/arch/arm/insts
parent186cfe3ae30970b43c09cccab6f004ea7d720838 (diff)
downloadgem5-6976b4890a307a2d8584b4e512e3f6d728e59ad5.tar.xz
ARM: Add a RegRegImmOp base class.
Diffstat (limited to 'src/arch/arm/insts')
-rw-r--r--src/arch/arm/insts/misc.cc12
-rw-r--r--src/arch/arm/insts/misc.hh17
2 files changed, 29 insertions, 0 deletions
diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc
index 87d3d1796..a5a4e3b32 100644
--- a/src/arch/arm/insts/misc.cc
+++ b/src/arch/arm/insts/misc.cc
@@ -206,6 +206,18 @@ RegRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
}
std::string
+RegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+ std::stringstream ss;
+ printMnemonic(ss);
+ printReg(ss, dest);
+ ss << ", ";
+ printReg(ss, op1);
+ ccprintf(ss, ", #%d", imm);
+ return ss.str();
+}
+
+std::string
RegRegImmImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
diff --git a/src/arch/arm/insts/misc.hh b/src/arch/arm/insts/misc.hh
index 79cec5732..53281400e 100644
--- a/src/arch/arm/insts/misc.hh
+++ b/src/arch/arm/insts/misc.hh
@@ -189,6 +189,23 @@ class RegRegRegOp : public PredOp
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
+class RegRegImmOp : public PredOp
+{
+ protected:
+ IntRegIndex dest;
+ IntRegIndex op1;
+ uint64_t imm;
+
+ RegRegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
+ IntRegIndex _dest, IntRegIndex _op1,
+ uint64_t _imm) :
+ PredOp(mnem, _machInst, __opClass),
+ dest(_dest), op1(_op1), imm(_imm)
+ {}
+
+ std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
class RegRegImmImmOp : public PredOp
{
protected: