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| author | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2017-01-12 17:59:44 +0000 |
|---|---|---|
| committer | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2017-12-05 11:47:01 +0000 |
| commit | 0c0ccad52595e837301eebcf8597862d9abb4f9c (patch) | |
| tree | 12192223452b33befcd472d980f23600d1d16c3d /src/arch/arm/insts | |
| parent | eeb36e5b6e81c6b9ea6a0c3c97573e762e58ae05 (diff) | |
| download | gem5-0c0ccad52595e837301eebcf8597862d9abb4f9c.tar.xz | |
arm: Add support for the dc {civac, cvac, cvau, ivac} instr
This patch adds support for decoding and executing the following ARMv8
cache maintenance instructions by Virtual Address:
* dc civac: Clean and Invalidate by Virtual Address to the Point
of Coherency
* dc cvac: Clean by Virtual Address to the Point of Coherency
* dc cvau: Clean by Virtual Address to the Point of Unification
* dc ivac: Invalidate by Virtual Addrsess to the Point of Coherency
Change-Id: I58cabda37f9636105fda1b1e84a0a04965fb5670
Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com>
Reviewed-by: Stephan Diestelhorst <stephan.diestelhorst@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5060
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/insts')
| -rw-r--r-- | src/arch/arm/insts/mem64.hh | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/arch/arm/insts/mem64.hh b/src/arch/arm/insts/mem64.hh index 933d34576..7ad2f52eb 100644 --- a/src/arch/arm/insts/mem64.hh +++ b/src/arch/arm/insts/mem64.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2013 ARM Limited + * Copyright (c) 2011-2013,2017 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -52,9 +52,9 @@ class SysDC64 : public ArmStaticInst uint64_t imm; SysDC64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, - IntRegIndex _base, IntRegIndex _dest, uint64_t _imm) - : ArmStaticInst(mnem, _machInst, __opClass), base(_base), dest(_dest), - imm(_imm) + IntRegIndex _base, MiscRegIndex miscReg, uint64_t _imm) + : ArmStaticInst(mnem, _machInst, __opClass), base(_base), + dest((IntRegIndex)miscReg), imm(_imm) {} std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; }; |