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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-05-13 17:27:01 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-05-13 17:27:01 -0500 |
| commit | 401165c778108ab22aeeee55c4f4451ca93bcffb (patch) | |
| tree | f525ba64108f6ebe208a04d2dee7b77621cafd96 /src/arch/arm/intregs.hh | |
| parent | e097c4fb188fafc9cd2253500ab2d056da886c9c (diff) | |
| download | gem5-401165c778108ab22aeeee55c4f4451ca93bcffb.tar.xz | |
ARM: Further break up condition code into NZ, C, V bits.
Break up the condition code bits into NZ, C, V registers. These are individually
written and this removes some incorrect dependencies between instructions.
Diffstat (limited to 'src/arch/arm/intregs.hh')
| -rw-r--r-- | src/arch/arm/intregs.hh | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/arch/arm/intregs.hh b/src/arch/arm/intregs.hh index 000c6306d..c26e36211 100644 --- a/src/arch/arm/intregs.hh +++ b/src/arch/arm/intregs.hh @@ -112,7 +112,9 @@ enum IntRegIndex INTREG_UREG0, INTREG_UREG1, INTREG_UREG2, - INTREG_CONDCODES_F, + INTREG_CONDCODES_NZ, + INTREG_CONDCODES_C, + INTREG_CONDCODES_V, INTREG_CONDCODES_GE, INTREG_FPCONDCODES, |