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| author | Ali Saidi <Ali.Saidi@arm.com> | 2010-08-23 11:18:40 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@arm.com> | 2010-08-23 11:18:40 -0500 |
| commit | 38cf6a164d7081f1a2f40ab210169681b4cd6929 (patch) | |
| tree | 98f3a6f7b4fdbb3f271f4a5b59302b85e6caa821 /src/arch/arm/isa.cc | |
| parent | b7b2eae6fa56a5b2923f8aa8cd7b5425d10163df (diff) | |
| download | gem5-38cf6a164d7081f1a2f40ab210169681b4cd6929.tar.xz | |
ARM: Implement some more misc registers
Diffstat (limited to 'src/arch/arm/isa.cc')
| -rw-r--r-- | src/arch/arm/isa.cc | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 17f95e57d..3a52919d4 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -212,6 +212,20 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc) break; case MISCREG_ID_PFR0: return 0x1031; // ThumbEE | !Jazelle | Thumb | ARM + case MISCREG_ID_MMFR0: + return 0x03; //VMSAz7 + case MISCREG_CTR: + return 0x86468006; // V7, 64 byte cache line, load/exclusive is exact + case MISCREG_ACTLR: + warn("Not doing anything for miscreg ACTLR\n"); + break; + case MISCREG_PMCR: + case MISCREG_PMCCNTR: + case MISCREG_PMSELR: + warn("Not doing anyhting for read to miscreg %s\n", + miscRegName[misc_reg]); + break; + } return readMiscRegNoEffect(misc_reg); } @@ -394,6 +408,15 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) case MISCREG_DTLBIASID: tc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); return; + case MISCREG_ACTLR: + warn("Not doing anything for write of miscreg ACTLR\n"); + break; + case MISCREG_PMCR: + case MISCREG_PMCCNTR: + case MISCREG_PMSELR: + warn("Not doing anything for write to miscreg %s\n", + miscRegName[misc_reg]); + break; case MISCREG_V2PCWPR: case MISCREG_V2PCWPW: case MISCREG_V2PCWUR: |