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AgeCommit message (Expand)Author
2018-06-11misc: Using smart pointers for memory RequestsGiacomo Travaglini
2018-05-29arch-arm: ISA param for treating MISCREG_IMPDEF_UNIMPL as NOPGiacomo Travaglini
2018-05-08arch-arm: Map ID_x_EL1 registers to AArch32 versionGiacomo Travaglini
2018-04-19arch-arm: Add ARMv8.1 TTBR1_EL2 registerGiacomo Travaglini
2018-04-18arch-arm: Fix masking in CPACR_EL1Chuan Zhu
2018-04-18arch-arm: Mask out unsupported trapped exception handling bitsChuan Zhu
2018-04-18arch-arm: Correct masking of cp10 and cp11 in CPACRChuan Zhu
2018-04-18arch-arm: Using explicit invalidation in TLBGiacomo Travaglini
2018-04-06arch-arm: Fix secure write of SCTLR when EL3 is AArch64Giacomo Travaglini
2018-03-23arch-arm: Distinguish IS TLBI from non-ISGiacomo Travaglini
2018-03-23arch-arm: Created function for TLB ASID InvalidationGiacomo Travaglini
2018-03-12arch-arm: Adding IPA-Based Invalidating instructionsGiacomo Travaglini
2018-03-12arch-arm: Implement missing aarch32 TLBI registersGiacomo Travaglini
2018-03-08arch-arm: Fix FSC generation in AbortFaultGiacomo Travaglini
2018-02-16arch-arm: Change ArmFault cast from reinterpret to staticGiacomo Travaglini
2018-02-08arch-arm: Don't change PSTATE in Illegal Exception returnGiacomo Travaglini
2018-01-29arch-arm: understandably initialize register permissionsCurtis Dunham
2018-01-29arm: extend MiscReg metadata structuresCurtis Dunham
2018-01-29arch-arm: understandably initialize register mappingsCurtis Dunham
2017-12-22arch,cpu: "virtualize" the TLB interface.Gabe Black
2017-12-14misc: Updates for gcc7.2 for x86Jason Lowe-Power
2017-07-05cpu: Added interface for vector reg fileRekai Gonzalez-Alberquilla
2017-02-09arm: AArch64 report cache size correctly when reading CTR_EL0Bjoern A. Zeeb
2016-11-09style: [patch 1/22] use /r/3648/ to reorganize includesBrandon Potter
2016-12-19arm: provide correct timer availability in ID_PFR1 registerCurtis Dunham
2016-12-19arm: compute ID_AA64PFR{0,1}_EL1 registersCurtis Dunham
2016-12-19arm: compute ID_PFR{0,1} registersCurtis Dunham
2016-12-19arm: miscreg refactoringCurtis Dunham
2016-12-19arm: audit SCTLRCurtis Dunham
2016-12-19arm: remove SCTLR.FICurtis Dunham
2016-12-19arm: update AArch{64,32} register mappingsCurtis Dunham
2016-08-15cpu, arch: fix the type used for the request flagsNikos Nikoleris
2016-08-02arm: Add TLBI instruction for stage 2 IPA'sDylan Johnson
2016-08-02arm: Fix EL perceived at TLB for address translation instructionsDylan Johnson
2016-08-02arm: add stage2 translation supportDylan Johnson
2016-08-02arm: enable EL2 supportCurtis Dunham
2016-08-02arm: invalidate TLB miscreg cache on modification of HSCTLRDylan Johnson
2016-07-11arm: Don't consult the TLB test iface for functional translationsAndreas Sandberg
2016-04-07mem: Remove threadId from memory request classMitch Hayenga
2016-04-06Revert power patch sets with unexpected interactionsAndreas Sandberg
2016-04-05mem: Remove threadId from memory request classMitch Hayenga
2015-10-09isa: Add parameter to pick different decoder inside ISARekai Gonzalez Alberquilla
2015-09-30isa,cpu: Add support for FS SMT InterruptsMitch Hayenga
2015-06-09arm: Delete debug print in initialization of hardware threadRune Holm
2015-05-23dev, arm: Refactor and clean up the generic timer modelAndreas Sandberg
2015-05-05arm: Remove unnecessary boot uncachabilityAndreas Hansson
2015-03-02arm: Don't truncate 16-bit ASIDs to 8 bitsAndreas Sandberg
2015-01-22mem: Clean up Request initialisationAndreas Hansson
2014-12-23arm: Add support for filtering in the PMUAndreas Sandberg
2014-10-29arm: Fix multi-system AArch64 boot w/caches.Ali Saidi
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