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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2010-06-02 12:58:16 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2010-06-02 12:58:16 -0500 |
| commit | c1e1de8d69624b1cf18a13a46e624ad5827954b7 (patch) | |
| tree | 60f11a14eafcc03715c283270edb336e0a44bccc /src/arch/arm/isa.cc | |
| parent | 7de7ea3b22e16a6d489a71dc5c54ddba5a5b5a0e (diff) | |
| download | gem5-c1e1de8d69624b1cf18a13a46e624ad5827954b7.tar.xz | |
ARM: Some TLB bug fixes.
Diffstat (limited to 'src/arch/arm/isa.cc')
| -rw-r--r-- | src/arch/arm/isa.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 3fcd25fe5..8446962a2 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -215,6 +215,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) break; case MISCREG_SCTLR: { + DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); SCTLR sctlr = miscRegs[MISCREG_SCTLR]; SCTLR new_sctlr = newVal; new_sctlr.nmfi = (bool)sctlr.nmfi; |