diff options
| author | Adrian Herrera <adrian.herrera@arm.com> | 2019-11-08 15:25:21 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-11-18 15:01:01 +0000 |
| commit | 17a0c0b00644c37e9d8539a9de0a02dc213a6834 (patch) | |
| tree | 8ab1d22fcfbc158dafc1a9e92a5d7562c820dc95 /src/arch/arm/isa.cc | |
| parent | 7e19b26f503435f07dc4b5675061facc521b8c91 (diff) | |
| download | gem5-17a0c0b00644c37e9d8539a9de0a02dc213a6834.tar.xz | |
arch-arm: R/W interface to AArch32 HCR2 misc reg
This patch implements read/write interfaces to HCR2 AArch32 register,
which is mapped to the upper 32 bits of HCR_EL2.
Change-Id: I996023f3ad8233457d19de8a506ebcf106409165
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22832
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/arch/arm/isa.cc')
| -rw-r--r-- | src/arch/arm/isa.cc | 11 |
1 files changed, 4 insertions, 7 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 712b43040..14cc993d1 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -479,12 +479,10 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc) switch (unflattenMiscReg(misc_reg)) { case MISCREG_HCR: - { + case MISCREG_HCR2: if (!haveVirtualization) return 0; - else - return readMiscRegNoEffect(MISCREG_HCR); - } + break; case MISCREG_CPACR: { const uint32_t ones = (uint32_t)(-1); @@ -1028,11 +1026,10 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) } break; case MISCREG_HCR: - { + case MISCREG_HCR2: if (!haveVirtualization) return; - } - break; + break; case MISCREG_IFSR: { // ARM ARM (ARM DDI 0406C.b) B4.1.96 |