summaryrefslogtreecommitdiff
path: root/src/arch/arm/isa.cc
AgeCommit message (Expand)Author
2020-02-04arch-arm: reg access permissions highest EL helperAdrian Herrera
2019-11-25arch-arm: default MIDR for Armv8 ISA processorsAdrian Herrera
2019-11-18arch-arm: R/W interface to AArch32 HCR2 misc regAdrian Herrera
2019-10-19arch: Make a base class for Interrupts.Gabe Black
2019-09-19arch-arm: PSTATE.PAN changes should inval cached regs in TLBGiacomo Travaglini
2019-09-06arch-arm: Fix read/setMiscReg for AArch32 GICv3 ICC regsGiacomo Travaglini
2019-08-07arch-arm: adding register control flags enabling LSE implementationJordi Vaquero
2019-08-05arch-arm: Implement ARMv8.1-PAN, Privileged access neverGiacomo Travaglini
2019-05-23arch-arm: Expose haveGicv3CPUInterface to the ISA interfaceGiacomo Travaglini
2019-04-25arch-arm: Remove un-needed hyp flag in TLBI operationsGiacomo Travaglini
2019-04-25arch-arm: Correct target EL field in TLBI operationsGiacomo Travaglini
2019-04-02dev-arm: Make GICv3 maintenance interrupt an ArmInterruptGiacomo Travaglini
2019-03-14arch-arm,cpu: Add initial support for Arm SVEGiacomo Gabrielli
2019-02-18arch-arm: Move GICv3 detection at startup timeGiacomo Travaglini
2019-01-25arch-arm: Inital vector rename mode depending on A32/A64Giacomo Travaglini
2019-01-22arch: cpu: Stop passing around misc registers by reference.Gabe Black
2019-01-22arm: Get rid of some register type definitions.Gabe Black
2019-01-16arch-arm: Read VMPIDR instead of MPIDR when EL2 is EnabledGiacomo Travaglini
2019-01-16arch-arm: Added TLBI_ALL EL2 instructionAnouk Van Laer
2019-01-10dev-arm: Add a GICv3 modelJairo Balart
2019-01-03arm: properly handle RES0/1 for SCTLRsCurtis Dunham
2018-12-19arch-arm: Add Crypto in SE modeGiacomo Travaglini
2018-11-14arch-arm: Print register name when warning on AT instructionsGiacomo Travaglini
2018-11-07arch-arm: ArmSystem::resetAddr64 renamed to be used in AArch32Giacomo Travaglini
2018-11-07arch-arm: Refactor ISA::clear by adding a ISA::clear32 methodGiacomo Travaglini
2018-10-09arch-arm: Add have_crypto System parameterGiacomo Travaglini
2018-10-01arch-arm: Implement AArch64 ID_AA64MMFR2_EL1 registerGiacomo Travaglini
2018-10-01arch-arm: Init AArch64 ID registers in SE modeGiacomo Travaglini
2018-09-10arm: Add support for tracking TCs in ISA devicesAndreas Sandberg
2018-07-16arch-arm: Introduce ARMv8.1 Virtual Timer System RegistersGiacomo Travaglini
2018-06-14arch-arm: Add Illegal Execution flag to PCStateGiacomo Travaglini
2018-06-11misc: Using smart pointers for memory RequestsGiacomo Travaglini
2018-05-29arch-arm: ISA param for treating MISCREG_IMPDEF_UNIMPL as NOPGiacomo Travaglini
2018-05-08arch-arm: Map ID_x_EL1 registers to AArch32 versionGiacomo Travaglini
2018-04-19arch-arm: Add ARMv8.1 TTBR1_EL2 registerGiacomo Travaglini
2018-04-18arch-arm: Fix masking in CPACR_EL1Chuan Zhu
2018-04-18arch-arm: Mask out unsupported trapped exception handling bitsChuan Zhu
2018-04-18arch-arm: Correct masking of cp10 and cp11 in CPACRChuan Zhu
2018-04-18arch-arm: Using explicit invalidation in TLBGiacomo Travaglini
2018-04-06arch-arm: Fix secure write of SCTLR when EL3 is AArch64Giacomo Travaglini
2018-03-23arch-arm: Distinguish IS TLBI from non-ISGiacomo Travaglini
2018-03-23arch-arm: Created function for TLB ASID InvalidationGiacomo Travaglini
2018-03-12arch-arm: Adding IPA-Based Invalidating instructionsGiacomo Travaglini
2018-03-12arch-arm: Implement missing aarch32 TLBI registersGiacomo Travaglini
2018-03-08arch-arm: Fix FSC generation in AbortFaultGiacomo Travaglini
2018-02-16arch-arm: Change ArmFault cast from reinterpret to staticGiacomo Travaglini
2018-02-08arch-arm: Don't change PSTATE in Illegal Exception returnGiacomo Travaglini
2018-01-29arch-arm: understandably initialize register permissionsCurtis Dunham
2018-01-29arm: extend MiscReg metadata structuresCurtis Dunham
2018-01-29arch-arm: understandably initialize register mappingsCurtis Dunham
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-07 17:11:36 +0000