diff options
author | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-12-19 11:03:27 -0600 |
---|---|---|
committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-12-19 11:03:27 -0600 |
commit | 282cf5807d827d5583e5cd5bffae75c4e5efb116 (patch) | |
tree | 5a6893f52b49478b3c2fb6214d0eedb73b249b7e /src/arch/arm/isa.cc | |
parent | 9cf6bc444b700bcf8140bb975e99cfdf13c3964c (diff) | |
download | gem5-282cf5807d827d5583e5cd5bffae75c4e5efb116.tar.xz |
arm: miscreg refactoring
Change-Id: I4e9e8f264a4a4239dd135a6c7a1c8da213b6d345
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/isa.cc')
-rw-r--r-- | src/arch/arm/isa.cc | 46 |
1 files changed, 14 insertions, 32 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 034340049..c093ceda9 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -226,12 +226,14 @@ ISA::ISA(Params *p) // Cache system-level properties if (FullSystem && system) { + highestELIs64 = system->highestELIs64(); haveSecurity = system->haveSecurity(); haveLPAE = system->haveLPAE(); haveVirtualization = system->haveVirtualization(); haveLargeAsid64 = system->haveLargeAsid64(); physAddrRange64 = system->physAddrRange64(); } else { + highestELIs64 = true; // ArmSystem::highestELIs64 does the same haveSecurity = haveLPAE = haveVirtualization = false; haveLargeAsid64 = false; physAddrRange64 = 32; // dummy value @@ -487,22 +489,10 @@ ISA::readMiscRegNoEffect(int misc_reg) const { assert(misc_reg < NumMiscRegs); - int flat_idx = flattenMiscIndex(misc_reg); // Note: indexes of AArch64 - // registers are left unchanged - MiscReg val; - - if (lookUpMiscReg[flat_idx].lower == 0 || flat_idx == MISCREG_SPSR) { - if (flat_idx == MISCREG_SPSR) - flat_idx = flattenMiscIndex(MISCREG_SPSR); - val = miscRegs[flat_idx]; - } else - if (lookUpMiscReg[flat_idx].upper > 0) - val = ((miscRegs[lookUpMiscReg[flat_idx].lower] & mask(32)) - | (miscRegs[lookUpMiscReg[flat_idx].upper] << 32)); - else - val = miscRegs[lookUpMiscReg[flat_idx].lower]; - - return val; + auto regs = getMiscIndices(misc_reg); + int lower = regs.first, upper = regs.second; + return !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32)) + |(miscRegs[upper] << 32)); } @@ -801,25 +791,17 @@ ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) { assert(misc_reg < NumMiscRegs); - int flat_idx = flattenMiscIndex(misc_reg); // Note: indexes of AArch64 - // registers are left unchanged - - int flat_idx2 = lookUpMiscReg[flat_idx].upper; - - if (flat_idx2 > 0) { - miscRegs[lookUpMiscReg[flat_idx].lower] = bits(val, 31, 0); - miscRegs[flat_idx2] = bits(val, 63, 32); + auto regs = getMiscIndices(misc_reg); + int lower = regs.first, upper = regs.second; + if (upper > 0) { + miscRegs[lower] = bits(val, 31, 0); + miscRegs[upper] = bits(val, 63, 32); DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n", - misc_reg, flat_idx, flat_idx2, val); + misc_reg, lower, upper, val); } else { - if (flat_idx == MISCREG_SPSR) - flat_idx = flattenMiscIndex(MISCREG_SPSR); - else - flat_idx = (lookUpMiscReg[flat_idx].lower > 0) ? - lookUpMiscReg[flat_idx].lower : flat_idx; - miscRegs[flat_idx] = val; + miscRegs[lower] = val; DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", - misc_reg, flat_idx, val); + misc_reg, lower, val); } } |